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hc11 microcontrollers freescale.com m68hc11e family data sheet m68hc11e rev. 5.1 07/2005

m68hc11e family data sheet, rev. 5.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc11e family data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location.
revision history m68hc11e family data sheet, rev. 5.1 4 freescale semiconductor revision history date revision level description page number(s) may, 2001 3.1 2.3.3.1 system configurat ion register ? addition to nocop bit description 44 added 10.21 eprom characteristics 175 june, 2001 3.2 10.21 eprom characteristics ? for clarity, addition to note 2 following the table 175 december, 2001 3.3 7.7.2 serial communications control register 1 ? sccr1 bit 4 (m) description corrected 110 july, 2002 4 10.7 mc68l11e9/e20 dc electrical characteristics ? title changed to include the mc68l11e20 153 10.8 mc68l11e9/e20 supply currents and power dissipation ? title changed to include the mc68l11e20 154 10.10 mc68l11e9/e20 control timing ? title changed to include the mc68l11e20 157 10.12 mc68l11e9/e20 peripheral port timing ? title changed to include the mc68l11e20 163 10.14 mc68l11e9/e20 analog-to-digital converter characteristics ? title changed to include the mc68l11e20 167 10.16 mc68l11e9/e20 expansion bus timing characteristics ? title changed to include the mc68l11e20 169 10.18 mc68l11e9/e20 serial peirpheral interface characteristics ? title changed to include the mc68l11e20 172 ? title changed to include the mc68l11e20 175 11.4 extended voltage device ordering information (3.0 vdc to 5.5 vdc) ? updated table to include mc68l1120 181 june, 2003 5 format updated to current pub lications standards throughout 1.4.6 non-maskable interrupt (xirq/ vppe) ? added caution note pertaining to eprom programming of the mc68hc711e9 device only. 23 6.4 port c ? clarified descr iption of ddrc[7:0] bits 100 10.21 eprom characteristics ? added note pertaining to eprom programming of the mc68hc711e9 device only. 175 july, 2005 5.1 updated to meet freescale identity guidelines. throughout
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 2 operating mo des and on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 chapter 3 analog-to-digital (a /d) converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 4 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 5 resets and interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 6 parallel input/output (i/o) po rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 7 serial communications interf ace (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 chapter 8 serial peripheral in terface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 9 timing systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 chapter 10 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 chapter 11 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 177 appendix a development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 appendix b evbu schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 an1060 ? m68hc11 b ootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 eb184 ? enabling the se curity feature on the mc68hc711e9 devices with pcbug11 on t he m68hc711e9pgmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 eb188 ? enabling the security f eature on m68hc811e2 devices with pcbug11 on t he m68hc711e9pgmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 eb296 ? programming mc68hc 711e9 devices with pcbug11 and the m68hc11evbu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
list of chapters m68hc11e family data sheet, rev. 5.1 6 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.3 crystal driver and external clock input (xtal and extal) . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.4 e-clock output (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.5 interrupt request (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.6 non-maskable interrupt (xirq /v ppe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.7 moda and modb (moda/lir and modb/v stby ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.7.1 v rl and v rh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.8 stra/as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.9 strb/r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.10 port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.10.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.10.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.10.3 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.10.4 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.10.5 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 chapter 2 operating modes and on-chip memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 single-chip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2 expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.3 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.4 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 ram and input/output mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.3 system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.3.1 system configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.3.3.2 ram and i/o mapping register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.3.3 system configuration options register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.1 programming an individual eprom address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.2 programming the eprom with downloaded data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
table of contents m68hc11e family data sheet, rev. 5.1 8 freescale semiconductor 2.4.3 eprom and eeprom programming contro l register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.5 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.1 eeprom and config programming and erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.1.1 block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.1.2 eprom and eeprom programming c ontrol register . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5.1.3 eeprom bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.5.1.4 eeprom row erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.5.1.5 eeprom byte erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.5.1.6 config register programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.5.2 eeprom security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 3 analog-to-digital (a/d) converter 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2 analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.3 digital control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.4 result registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.5 a/d converter clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.6 conversion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 a/d converter power-up and clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 conversion process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5 channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.6 single-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7 multiple-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.8 operation in stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.9 a/d control/status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.10 a/d converter result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 chapter 4 central processor unit (cpu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2.1 accumulators a, b, and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.2 index register x (ix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.3 index register y (iy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.6 condition code register (ccr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 4.2.6.1 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.6.2 overflow (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.6.3 zero (z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.6.4 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.6.5 interrupt mask (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.6.6 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.6.7 x interrupt mask (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.6.8 stop disable (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 9 4.3 data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4 opcodes and operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.1 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.3 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.5.4 indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.5.5 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.5.6 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 chapter 5 resets and interrupts 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.2 external reset (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.2.3 computer operating properly (cop) reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.2.4 clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2.5 system configuration options register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2.6 configuration control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.1 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.3 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.4 real-time interrupt (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.5 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.6 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.7 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.9 analog-to-digital (a/d) converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.10 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.4 reset and interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.4.1 highest priority interrupt and miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.5.1 interrupt recognition and register stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.5.2 non-maskable interrupt request (xirq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.5.3 illegal opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.5.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5.5 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5.6 reset and interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
table of contents m68hc11e family data sheet, rev. 5.1 10 freescale semiconductor chapter 6 parallel input/output (i/o) ports 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.7 handshake protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.8 parallel i/o control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 chapter 7 serial communications interface (sci) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.3 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.4 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5 wakeup feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.1 idle-line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.2 address-mark wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6 sci error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.7 sci registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.7.1 serial communications data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.7.2 serial communications control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.7.3 serial communications control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.7.4 serial communication status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.7.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.8 status flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.9 receiver flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 8 serial peripheral interface (spi) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3 spi transfer formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.4 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.5 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5.1 master in/slave out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5.2 master out/slave in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.5.4 slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.6 spi system errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.7 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.7.1 serial peripheral control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 8.7.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 8.7.3 serial peripheral data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 11 chapter 9 timing systems 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.2 timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.3 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.3.1 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.3.2 timer input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 31 9.3.3 timer input capture 4/output compare 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.4.1 timer output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.2 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.3 output compare mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.4.4 output compare data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.4.5 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4.6 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4.7 timer interrupt mask 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 9.4.8 timer interrupt flag 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.9 timer interrupt mask 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 9.4.10 timer interrupt flag register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5 real-time interrupt (rti). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5.1 timer interrupt mask register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 41 9.5.2 timer interrupt flag register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.3 pulse accumulator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6 computer operating properly (cop) watchdog function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.7 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.7.1 pulse accumulator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.7.2 pulse accumulator count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.7.3 pulse accumulator status and interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 chapter 10 electrical characteristics 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.2 maximum ratings for standard and extended voltage devices . . . . . . . . . . . . . . . . . . . . . . . 149 10.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.6 supply currents and power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.7 mc68l11e9/e20 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.8 mc68l11e9/e20 supply currents and power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.9 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.10 mc68l11e9/e20 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.11 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.12 mc68l11e9/e20 peripheral port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.13 analog-to-digital converter characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 66 10.14 mc68l11e9/e20 analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . 167
table of contents m68hc11e family data sheet, rev. 5.1 12 freescale semiconductor 10.15 expansion bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 68 10.16 mc68l11e9/e20 expansion bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.17 serial peripheral interface timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.18 mc68l11e9/e20 serial peirpheral interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.19 eeprom characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.20 mc68l11e9/e20 eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.21 eprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 chapter 11 ordering information and m echanical specifications 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.2 standard device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 11.3 custom rom device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.4 extended voltage device ordering information (3.0 vdc to 5.5 vdc) . . . . . . . . . . . . . . . . . . . 181 11.5 52-pin plastic-leaded chip carrier (case 778). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.6 52-pin windowed ceramic-leaded chip carrier (case 778b) . . . . . . . . . . . . . . . . . . . . . . . . 183 11.7 64-pin quad flat pack (case 840c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 11.8 52-pin thin quad flat pack (case 848d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.9 56-pin dual in-line package (case 859). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.10 48-pin plastic dip (case 767) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 appendix a development support a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 a.2 m68hc11 e-series development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 a.3 evs ? evaluation system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 a.4 modular development system (mmds11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 a.5 spgmr11 ? serial programmer for m68hc11 mcus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 appendix b evbu schematic an1060 ? m68hc11 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 eb184 ? enabling the security feature on the mc68hc711e9 devices with pcbug11 on the m68hc711e9pgmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 eb188 ? enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 eb296 ? programming mc68hc711e9 devices with pcbug11 and the m68hc11evbu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 13 chapter 1 general description 1.1 introduction this document contains a detailed description of t he m68hc11 e series of 8-bit microcontroller units (mcus). these mcus all combine the m68hc11 cent ral processor unit (cpu) with high-performance, on-chip peripherals. the e series is comprised of many dev ices with various configurations of: random-access memory (ram) read-only memory (rom) erasable programmable read-only memory (eprom) electrically erasable programm able read-only memory (eeprom) several low-voltage devices are also available. with the exception of a few minor differences, the operati on of all e-series mcus is identical. a fully static design and high-density complementary metal-oxi de semiconductor (hcmos) fabrication process allow the e-series devices to operate at frequencies from 3 mhz to dc with very low power consumption. 1.2 features features of the e-series devices include: m68hc11 cpu power-saving stop and wait modes low-voltage devices available (3.0?5.5 vdc) 0, 256, 512, or 768 bytes of on-chip ram, data retained during standby 0, 12, or 20 kbytes of on-chip rom or eprom 0, 512, or 2048 bytes of on-chip eeprom with block protect for security 2048 bytes of eeprom with select able base address in the mc68hc811e2 asynchronous non-return-to-zero (nrz) serial communications interface (sci) additional baud rates available on mc68hc(7)11e20 synchronous serial peripheral interface (spi) 8-channel, 8-bit analog-to-digital (a/d) converter 16-bit timer system: ? three input capture (ic) channels ? four output compare (oc) channels ? one additional channel, selectable as fourth ic or fifth oc 8-bit pulse accumulator real-time interrupt circuit
general description m68hc11e family data sheet, rev. 5.1 14 freescale semiconductor computer operating properly (cop) watchdog system 38 general-purpose input/output (i/o) pins: ? 16 bidirectional i/o pins ? 11 input-only pins ? 11 output-only pins several packaging options: ? 52-pin plastic-leaded chip carrier (plcc) ? 52-pin windowed ceramic leaded chip carrier (clcc) ? 52-pin plastic thin quad flat pack, 10 mm x 10 mm (tqfp) ? 64-pin quad flat pack (qfp) ? 48-pin plastic dual in-line package (dip), mc68hc811e2 only ? 56-pin plastic shrink dual in-line package, .070-inch lead spacing (sdip) 1.3 structure see figure 1-1 for a functional diagram of the e-series mcus. differences among devices are noted in the table accompanying figure 1-1 . 1.4 pin descriptions m68hc11 e-series mcus are available packaged in: 52-pin plastic-leaded chip carrier (plcc) 52-pin windowed ceramic leaded chip carrier (clcc) 52-pin plastic thin quad flat pack, 10 mm x 10 mm (tqfp) 64-pin quad flat pack (qfp) 48-pin plastic dual in-line package (dip), mc68hc811e2 only 56-pin plastic shrink dual in-line package, .070-inch lead spacing (sdip) most pins on these mcus serve two or more functi ons, as described in the following paragraphs. refer to figure 1-2 , figure 1-3 , figure 1-4 , figure 1-5 , and figure 1-6 which show the m68hc11 e-series pin assignments for the plcc/clcc, qf p, tqfp, sdip, and dip packages.
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 15 figure 1-1. m68hc11 e-series block diagram pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc4/addr4/data4 pc3/addr3/data3 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 mode control osc clock logic interrupt logic eeprom (see table) ram (see table) serial peripheral interface spi serial communication interface sci m68hc11 cpu a/d converter control port d port e pe7/an7 txd rxd ss sck mosi miso pd5/ss pd0/rxd stra/as strb/r/w address/data bus expansion address as strobe and handshake parallel i/o strb stra control port c port b pb7/addr15 port a pa7/pai timer system cop pulse accumulator oc2 oc3 oc4 oc5/ic4/oc1 ic1 ic2 ic3 pai periodic interrupt moda/ lir modb/ v stby xtal extal e irq xirq /v ppe* reset pd4/sck pd3/mosi pd2/miso pd1/txd r/w pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 pa2/ic1 pa1/ic2 pa0/ic3 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe6/an6 pe5/an5 pe4/an4 pe3/an3 pe2/an2 pe1/an1 pe0/an0 v dd v ss v rh v rl * v ppe applies only to devices with eprom/otprom. rom or eprom (see table) mc68hc11e0 device 512 512 512 512 768 768 ram ? ? 12 k ? 20 k ? rom ? ? ? 12 k ? 20 k eprom ? 512 512 512 512 512 eeprom mc68hc11e1 mc68hc11e9 mc68hc711e9 mc68hc11e20 mc68hc711e20 256 ? ? 2048 mc68hc811e2
general description m68hc11e family data sheet, rev. 5.1 16 freescale semiconductor figure 1-2. pin assignments for 52-pin plcc and clcc pe4/an4 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 extal strb/r/w e stra/as moda/lir modb/v stby v ss v rh v rl pe7/an7 pe3/an3 xtal pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset * xirq /v ppe pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 m68hc11 e series 8 9 10 11 12 13 14 15 16 17 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 7 6 5 4 3 1 2 52 51 50 49 irq 18 pd0/rxd 19 pa2/ic1 32 pa1/ic2 33 pe6/an6 48 pe2/an2 47 pe1/an1 45 pe5/an5 46 20 * v ppe applies only to devices with eprom/otprom.
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 17 figure 1-3. pin assignments for 64-pin qfp pa0/ic3 nc nc nc pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe4/an4 pe1/an1 pe5/an5 pe2/an2 pe6/an6 pe3/an3 pe7/an7 v rl v rh v ss v ss modb/v stby moda/lir nc stra/as e strb/r/w nc nc pd0/rxd irq xirq /v ppe (1) nc reset pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc3/addr3/data3 pc4/addr4/data4 pc2/addr2/data2 pc1/addr1/data1 nc pc0/addr0/data0 xtal pa1/ic2 pa2/ic1 pa3/oc5/ic4/oc1 nc nc pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 pd5/ss v dd pd4/sck pd3/mosi pd2/miso pd1/txd v ss m68hc11 e series 64 1 2 3 4 5 6 7 8 9 17 18 19 20 21 22 23 24 25 27 63 62 61 60 59 58 57 56 54 10 11 48 47 46 45 44 43 42 41 40 38 39 55 26 12 13 14 15 16 37 36 35 34 33 28 29 30 31 32 53 52 51 50 49 extal 1. v ppe applies only to devices with eprom/otprom.
general description m68hc11e family data sheet, rev. 5.1 18 freescale semiconductor figure 1-4. pin assignments for 52-pin tqfp pa0/ic3 pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe4/an4 pe1/an1 pe5/an5 pa1/ic2 pa2/ic1 pa3/oc5/ic4/oc1 pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 pd5/ss v dd pd4/sck pd3/mosi pd2/miso m68hc11 e series 52 1 2 3 4 5 6 7 8 9 51 50 49 48 47 46 45 44 42 10 11 43 12 13 41 40 pe2/an2 pe6/an6 pe3/an3 pe7/an7 v rl v rh v ss modb/v stby moda/lir stra/as e strb/r/w extal 14 15 16 17 18 19 20 21 22 24 23 25 26 pd0/rxd irq xirq /v ppe (1) reset pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc3/addr3/data3 pc4/addr4/data4 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 xtal 39 38 37 36 35 34 33 32 31 29 30 28 27 pd1/txd 1. v ppe applies only to devices with eprom/otprom.
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 19 figure 1-5. pin assignments for 56-pin sdip * v ppe applies only to devices with eprom/otprom. pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset * xirq /v ppe m68hc11 e series 9 10 11 12 13 14 15 16 17 18 irq 19 pd0/rxd 20 21 pd1/txd 22 pd2/miso 23 pd3/mosi 24 pd4/sck 25 pd5/ss 26 v dd 27 v ss 28 xtal 8 extal 7 strb/r/w 6 5 stra/as 4 moda/lir 3 modb/v stby 2 v ss 1 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 pa1/ic2 46 45 44 43 42 41 40 39 38 37 36 pe4/an4 47 pe1/an1 48 pa2/ic1 35 pa3/oc5/ic4/oc1 34 pa4/oc4/oc1 33 pa5/oc3/oc1 32 pa6/oc2/oc1 31 pa7/pai/oc1 30 ev dd 29 pe5/an5 49 pe2/an2 50 pe6/an6 51 pe3/an3 52 pe7/an7 53 v rl 54 v rh 55 ev ss 56 ev ss e
general description m68hc11e family data sheet, rev. 5.1 20 freescale semiconductor figure 1-6. pin assignments for 48-pin dip (mc68hc811e2) pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe1/an1 mc68hc811e2 9 10 11 12 13 14 15 16 17 18 pe2/an2 19 pe3/an3 20 21 v rh 22 v ss 23 modb/v stby 24 pa0/ic3 8 pa1/ic2 7 pa2/ic1 6 pa3/oc5/ic4/oc1 5 pa4/oc4/oc1 4 pa5/oc3/oc1 3 pa6/oc2/oc1 2 pa7/pai/oc1 1 pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc4/addr4/data4 pc3/addr3/data3 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 xtal extal strb/r/w 38 37 36 35 34 33 32 31 30 29 28 reset 39 xirq 40 e 27 stra/as 26 moda/lir 25 irq 41 pd0/rxd 42 pd1/txd 43 pd2/miso 44 pd3/mosi 45 pd4/sck 46 pd5/ss 47 v dd 48 v rl
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 21 1.4.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is the power supply, v ss is ground. the mcu operates from a single 5-volt (nominal) power supp ly. low-voltage devices in the e series operate at 3.0?5.5 volts. very fast signal transitions occur on the mcu pins. th e short rise and fall times place high, short duration current demands on the power supply. to prevent noise problems, provide go od power supply bypassing at the mcu. also, use bypass capacitors that have good high-frequency characteristics and si tuate them as close to the mcu as possible. bypass requirements vary, depending on how heavily the mcu pins are loaded. figure 1-7. external reset circuit figure 1-8. external reset circuit with delay 4.7 k ? to reset v dd mc34(0/1)64 reset gnd in of m68hc11 2 1 3 v dd to reset v dd mc34064 reset gnd in of m68hc11 reset gnd in manual reset switch 4.7 k ? 1.0 f mc34164 4.7 k ? v dd v dd optional power-on delay and manual reset switch 4.7 k ?
general description m68hc11e family data sheet, rev. 5.1 22 freescale semiconductor 1.4.2 reset a bidirectional control signal, reset , acts as an input to initialize the mcu to a known startup state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (cop) watchdog circuit. the cpu distinguishes between internal and external reset conditions by sens ing whether the reset pin rises to a logic 1 in less than two e-clock cycles after a reset has occurred. see figure 1-7 and figure 1-8 . caution do not connect an external resistor capacitor (rc) power-up delay circuit to the reset pin of m68hc11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. because the cpu is not able to fetch and execute instructions properly when v dd falls below the minimum operating voltage level, reset must be controlled. a low-voltage inhibit (lvi) circuit is required primarily for protection of eeprom contents. however, since the c onfiguration register (config) value is read from the eeprom, protection is required even if the eeprom array is not being used. presently, there are several economical ways to so lve this problem. for exam ple, two good external components for lvi reset are: 1. the seiko s0854hn (or other s805 series devices): a. extremely low power (2 a) a. to-92 package a. limited temperature range, ?20 c to +70 c a. available in various trip-point voltage ranges 2. the freescale mc34064: a. to-92 or so-8 package a. draws about 300 a a. temperature range ?40 c to 85 c a. well controlled trip point a. inexpensive refer to chapter 5 resets and interrupts for further information. 1.4.3 crystal driver and external clock input (xtal and extal) these two pins provide the interface for either a cr ystal or a cmos- compatible clock to control the internal clock generator circuitry. the frequency applied to these pins is four times higher than the desired e-clock rate. the xtal pin must be left unterminated when an external cmos- compatible clock input is connected to the extal pin. the xtal output is normally intended to drive only a crystal. refer to figure 1-9 and figure 1-10 . caution in all cases, use caution around the oscillator pins. load capacitances shown in the oscillator circuit are spec ified by the crystal manufacturer and should include all stray layout capacitances.
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 23 figure 1-9. common parallel resonant crystal connections figure 1-10. external oscillator connections 1.4.4 e-clock output (e) e is the output connection for the internally generat ed e clock. the signal from e is used as a timing reference. the frequency of the e-clock output is one fourth that of the input frequency at the xtal and extal pins. when e-clock output is low, an internal pr ocess is taking place. when it is high, data is being accessed. all clocks, including the e clock, are halted when the mcu is in stop mode. to reduce rfi emissions, the e-clock output of most e-series devices can be disabled while operating in single-chip modes. the e-clock signal is always enabled on the mc68hc811e2. 1.4.5 interrupt request (irq ) the irq input provides a means of applying asynchronous interrupt requests to the mcu. either negative edge-sensitive triggering or level-sensitive trigger ing is program selectable (option register). irq is always configured to level-sensitive triggering at reset. when using irq in a level-sensitive wired-or configuration, connect an external pullup resistor, typically 4.7 k ? , to v dd . 1.4.6 non-maskabl e interrupt (xirq /v ppe ) the xirq input provides a means of requesting a non-maskabl e interrupt after reset initialization. during reset, the x bit in the condition code register (ccr) is set and any interrupt is masked until mcu software enables it. because the xirq input is level-sensitive, it can be connected to a multiple-source wired-or network with an external pullup resistor to v dd . xirq is often used as a power loss detect interrupt. whenever xirq or irq is used with multiple interrupt sources each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. 10 m ? mcu c l c l extal xtal 4 x e crystal nc mcu extal xtal 4 x e cmos-compatible external oscillator
general description m68hc11e family data sheet, rev. 5.1 24 freescale semiconductor note irq must be configured for level-sensitive operation if there is more than one source of irq interrupt. there should be a single pullup resistor near the mcu interrupt input pin (typically 4.7 k ? ). there must also be an interlock mechanism at each interrupt sour ce so that the source holds the interrupt line low until the mcu recognizes and acknowledges the interrupt request. if one or more interrupt sources are still pending after the mcu services a request, the interrupt line will still be held low and the mcu will be interrupted again as soon as the interrupt mask bit in the mcu is cleared (normally upon return from an interrupt). refer to chapter 5 resets and interrupts . v ppe is the input for the 12-volt nominal pr ogramming voltage required for eprom/otprom programming. on devices without eprom /otprom, this pin is only an xirq input. caution during eprom programming of t he mc68hc711e9 device, the v ppe pin circuitry may latch-up and be damaged if the input current is not limited to 10 ma. for more information please refer to mc68hc711e9 8-bit microcontroller unit mask set errata 3 (freescale document order number 68hc711e9mse3. 1.4.7 moda and modb (moda/lir and modb/v stby ) during reset, moda and modb select one of the four operating modes: single-chip mode expanded mode test mode bootstrap mode refer to chapter 2 operating modes and on-chip memory . after the operating mode has been selected, the load instruction register (lir ) pin provides an open-drain output to indicate that execution of an instruction has begun. a series of e-clock cycles occurs during execution of each instruction. the lir signal goes low during the first e-clock cycle of each instruction (opcode fetch). this output is provided for assistance in program debugging. the v stby pin is used to input random-access memory (ram) standby power. when the voltage on this pin is more than one mos threshold (about 0.7 volts) above the v dd voltage, the internal ram and part of the reset logic are powered from this signal rather than the v dd input. this allows ram contents to be retained without v dd power applied to the mcu. reset must be driven low before v dd is removed and must remain low until v dd has been restored to a valid level. 1.4.8 v rl and v rh these two inputs provide the reference voltages fo r the analog-to-digital (a/d) converter circuitry: v rl is the low reference, typically 0 vdc. v rh is the high reference. for proper a/d converter operation: v rh should be at least 3 vdc greater than v rl . v rl and v rh should be between v ss and v dd .
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 25 1.4.9 stra/as the strobe a (stra) and address strobe (as) pin perf orms either of two separate functions, depending on the operating mode: in single-chip mode, stra performs an input handshake (strobe input) function. in the expanded multiplexed mode, as provides an address strobe function. as can be used to demultiplex the address and data signals at port c. refer to chapter 2 operating modes and on-chip memory . 1.4.10 strb/r/w the strobe b (strb) and read/write (r/w ) pin act as either an output strobe or as a data bus direction indicator, depending on the operating mode. in single-chip operating mode, strb acts as a pr ogrammable strobe for handshake with other parallel devices. refer to chapter 6 parallel input/output (i/o) ports for further information. in expanded multiplexed operating mode, r/w is used to indicate the direction of transfers on the external data bus. a low on the r/w pin indicates data is being written to the external data bus. a high on this pin indicates that a read cycle is in progress. r/w stays low during consecutive data bus write cycles, such as a double-byte store. it is possible for data to be driven out of port c, if internal read visibility (irv) is enabled and an internal address is read, even though r/w is in a high-impedance state. refer to chapter 2 operating m odes and on-chip memory for more information about irvne (internal read visibility not e). 1.4.11 port signals port pins have different functions in different operati ng modes. pin functions for port a, port d, and port e are independent of operating modes. port b and port c, however, are affected by operating mode. port b provides eight general-purpose output signals in single-chip operat ing modes. when the microcontroller is in expanded multiplexed operating mode, port b pins are the eight high-order address lines. port c provides eight general-purpose input/output sign als when the mcu is in the single-chip operating mode. when the microcontroller is in the expanded multiplexed operating mode, port c pins are a multiplexed address/data bus. refer to table 1-1 for a functional description of the 40 port signals within different operating modes. terminate unused inputs and input/output (i/o) pins configured as inputs high or low. 1.4.12 port a in all operating modes, port a can be configured for thr ee timer input capture (ic) functions and four timer output compare (oc) functions. an additional pin can be configured as either the fourth ic or the fifth oc. any port a pin that is not currently being used for a ti mer function can be used as either a general-purpose input or output line. only port a pins pa7 and pa3 have an associated data direction control bit that allows the pin to be selectively configured as input or out put. bits ddra7 and ddra3 located in pactl register control data direction for pa7 and pa3, respectively. all other port a pins are fixed as either input or output. pa7 can function as general-purpose i/o or as timer out put compare for oc1. pa7 is also the input to the pulse accumulator, even while functioning as a general-purpose i/o or an oc1 output.
general description m68hc11e family data sheet, rev. 5.1 26 freescale semiconductor table 1-1. port signal functions port/bit single-chip and bootstrap modes expanded and test modes pa 0 pa 0 / i c 3 pa 1 pa 1 / i c 2 pa 2 pa 2 / i c 1 pa3 pa3/oc5/ic4/oc1 pa4 pa4/oc4/oc1 pa5 pa5/oc3/oc1 pa6 pa6/oc2/oc1 pa7 pa7/pai/oc1 pb0 pb0 addr8 pb1 pb1 addr9 pb2 pb2 addr10 pb3 pb3 addr11 pb4 pb4 addr12 pb5 pb5 addr13 pb6 pb6 addr14 pb7 pb7 addr15 pc0 pc0 addr0/data0 pc1 pc1 addr1/data1 pc2 pc2 addr2/data2 pc3 pc3 addr3/data3 pc4 pc4 addr4/data4 pc5 pc5 addr5/data5 pc6 pc6 addr6/data6 pc7 pc7 addr7/data7 pd0 pd0/rxd pd1 pd1/txd pd2 pd2/miso pd3 pd3/mosi pd4 pd4/sck pd5 pd5/ss ? stra as ?strb r/w pe0 pe0/an0 pe1 pe1/an1 pe2 pe3/an2 pe3 pe3/an3 pe4 pe4/an4 pe5 pe5/an5 pe6 pe6/an6 pe7 pe7/an7
pin descriptions m68hc11e family data sheet, rev. 5.1 freescale semiconductor 27 pa6?pa4 serve as either general-purpose outputs, timer input captures, or timer output compare 2?4. in addition, pa6?pa4 can be controlled by oc1. pa3 can be a general-purpose i/o pin or a timer ic/oc pin. timer functions associated with this pin include oc1 and ic4/oc5. ic4/oc5 is software selectable as either a fourth input capture or a fifth output compare. pa3 can also be configured to allow oc1 edges to trigger ic4 captures. pa2?pa0 serve as general-purpose inputs or as ic1?ic3. porta can be read at any time. reads of pins confi gured as inputs return the logic level present on the pin. pins configured as outputs return the logic level present at the pin driver input. if written, porta stores the data in an internal latch, bits 7 and 3. it drives the pins only if they are configured as outputs. writes to porta do not change the pin state when pins are configured for timer input captures or output compares. refer to chapter 6 parallel input/output (i/o) ports . 1.4.13 port b during single-chip operating modes, all port b pins are general-purpose output pins. during mcu reads of this port, the level sensed at the input side of the port b output drivers is read. port b can also be used in simple strobed output mode. in this mode, an output pulse appears at the strb signal each time data is written to port b. in expanded multiplexed operating modes, all of the por t b pins act as high order address output signals. during each mcu cycle, bits 15?8 of the address bus are output on the pb7?pb0 pins. the portb register is treated as an external address in expanded modes. 1.4.14 port c while in single-chip operating modes, all port c pins are general-purpose i/o pins. port c inputs can be latched into an alternate portcl register by providing an input transition to the stra signal. port c can also be used in full handshake m odes of parallel i/o where the stra input and strb output act as handshake control lines. when in expanded multiplexed modes, all port c pins ar e configured as multiplexed address/data signals. during the address portion of each mcu cycle, bits 7?0 of the address are output on the pc7?pc0 pins. during the data portion of each mcu cycle (e high), pc7?pc0 are bidirectional data signals, data7?data0. the direction of data at t he port c pins is indicated by the r/w signal. the cwom control bit in the pioc register disables the port c p-channel output driver. cwom simultaneously affects all eight bits of port c. be cause the n-channel driver is not affected by cwom, setting cwom causes port c to become an open-drai n type output port suitable for wired-or operation. in wired-or mode: when a port c bit is at logic level 0, it is driven low by the n-channel driver. when a port c bit is at logic level 1, the associated pin has high-impedance, as neither the n-channel nor the p-channel devices are active. it is customary to have an external pullup resistor on lines that are driven by open-drain devices. port c can only be configured for wired-or operation when the mcu is in single-chip mode. refer to chapter 6 parallel input/output (i/o) ports for additional informati on about port c functions.
general description m68hc11e family data sheet, rev. 5.1 28 freescale semiconductor 1.4.15 port d pins pd5?pd0 can be used for general-purpose i/o sig nals. these pins alternately serve as the serial communication interface (sci) and serial peripheral in terface (spi) signals when those subsystems are enabled. pd0 is the receive data input (rxd) signal for the sci. pd1 is the transmit data output (txd) signal for the sci. pd5?pd2 are dedicated to the spi: ? pd2 is the master in/slave out (miso) signal. ? pd3 is the master out/slave in (mosi) signal. ? pd4 is the serial clock (sck) signal. ? pd5 is the slave select (ss ) input. 1.4.16 port e use port e for general-purpose or analog-to-digital (a/d) inputs. caution if high accuracy is required for a/d conversions, avoid reading port e during sampling, as small disturbances can reduce the accuracy of that result.
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 29 chapter 2 operating modes and on-chip memory 2.1 introduction this section contains information about the oper ating modes and the on-chip memory for m68hc11 e-series mcus. except for a few minor differences, oper ation is identical for all devices in the e series. differences are noted where necessary. 2.2 operating modes the values of the mode select inputs modb and moda during reset determine the operating mode. single-chip and expanded multiplexed are the normal modes. in single-chip mode only on-chip memory is available. expanded mode, however, allows access to external memory. each of the two normal modes is paired with a special mode: bootstrap, a variation of the single-chip mode, is a special mode that executes a bootloader program in an internal bootstrap rom. test is a special mode that allows privileged access to internal resources. 2.2.1 single-chip mode in single-chip mode, ports b and c and strobe pi ns a (stra) and b (strb) are available for general-purpose parallel input/output (i/o). in this mode, all software needed to control the mcu is contained in internal resources. if present, read-on ly memory (rom) and/or erasable, programmable read-only memory (eprom) will al ways be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations $ffc0?$ffff. note for the mc68hc811e2, the vector locations are the same; however, they are contained in the 2048-byte eeprom array. 2.2.2 expanded mode in expanded operating mode, the mcu can access th e full 64-kbyte address space. the space includes: the same on-chip memory addresses used for single-chip mode addresses for external peripherals and memory devices the expansion bus is made up of ports b and c, and control signals as (address strobe) and r/w (read/write). r/w and as allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. during the first half of each bus cycle address information is present. during the second half of each bus cycle the pins become th e bidirectional data bus. as is an active-high latch enable signal for an external address latch. address information is a llowed through the transparent latch while as is high and is latched when as drives low.
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 30 freescale semiconductor the address, r/w , and as signals are active and valid for all bus cycles, including accesses to internal memory locations. the e clock is used to enable exte rnal devices to drive data onto the internal data bus during the second half of a read bus cycle (e clock high). r/w controls the direction of data transfers. r/w drives low when data is being written to the internal data bus. r/w will remain low during consecutive data bus write cycles, such as when a double-byte store occurs. refer to figure 2-1 . note the write enable signal for an external memory is the nand of the e clock and the inverted r/w signal. figure 2-1. address/data demultiplexing 2.2.3 test mode test mode, a variation of the expanded mode, is pr imarily used during freescale?s internal production testing; however, it is accessible for programming the configuration (confi g) register, programming calibration data into electrically erasable, progra mmable read-only memory (eeprom), and supporting emulation and debugging during development. 2.2.4 bootstrap mode when the mcu is reset in special bootstrap mode, a small on-chip read-only memory (rom) is enabled at address $bf00?$bfff. the rom contains a bootl oader program and a special set of interrupt and reset vectors. the mcu fetches the reset vector, then executes the bootloader. bootstrap mode is a special variation of the single- chip mode. bootstrap mode allows special-purpose programs to be entered into internal random-acces s memory (ram). when bootstrap mode is selected at reset, a small bootstrap rom becomes present in the memory map. reset and interrupt vectors are hc373 mcu addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr15 addr6 addr5 addr4 addr3 addr2 addr1 addr0 addr7 data6 data5 data4 data3 data2 data1 data0 data7 d2 d3 d4 d5 d6 d7 d8 d1 q2 q3 q4 q5 q6 q7 q8 q1 oe le pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc7 as pb6 pb5 pb4 pb3 pb2 pb1 pb0 pb7 r/w e we oe
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 31 located in this rom at $bfc0?$bfff. the bootstrap rom contains a small program which initializes the serial communications interface (sci) and allows th e user to download a program into on-chip ram. the size of the downloaded program can be as large as the si ze of the on-chip ram. after a 4-character delay, or after receiving the character for the highest addres s in ram, control passes to the loaded program at $0000. refer to figure 2-2 , figure 2-3 , figure 2-4 , figure 2-5 , and figure 2-6 . use of an external pullup resistor is required when us ing the sci transmitter pin because port d pins are configured for wired-or operation by the bootloader. in bootstrap mode, the interrupt vectors are directed to ram. this allows the use of interrupts through a jump table. refer to the application note an1060 entitled m68hc11 bootstrap mode , that is included in this data book . 2.3 memory map the operating mode determines memory mapping and whether external addresses can be accessed. refer to figure 2-2 , figure 2-3 , figure 2-4 , figure 2-5 , and figure 2-6 , which illustrate the memory maps for each of the three families comprising the m68hc11 e series of mcus. memory locations for on-chip resources are the same for both expanded and single-chip modes. control bits in the configuration (config) register allo w eprom and eeprom (if present) to be disabled from the memory map. the ram is mapped to $0000 after reset. it can be placed at any 4-kbyte boundary ($x000) by writing an appropriate value to the ram an d i/o map register (init). the 64-byte register block is mapped to $1000 after reset and also can be placed at any 4-kbyte boundary ($x000) by writing an appropriate value to the init register. if ram and registers are mapped to the same boundary, the first 64 bytes of ram will be inaccessible. refer to figure 2-7 , which details the mcu register and contro l bit assignments. reset states shown are for single-chip mode only. figure 2-2. memory map for mc68hc11e0 ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram bootstrap special test ext 0000 1000 103f bf00 expanded bfff bfc0 bfff special modes interrupt vectors boot rom ext ext 01ff ext $0000 $1000 $b600 $d000 $ffff
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 32 freescale semiconductor figure 2-3. memory map for mc68hc11e1 figure 2-4. memory map for mc68hc(7)11e9 ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom boot rom ext ext ext 01ff ext ext ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram single chip bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded d000 ffff bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom 12 kbytes rom/eprom boot rom ext ext ext 01ff ext ext
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 33 figure 2-5. memory map for mc68hc(7)11e20 figure 2-6. memory map for mc68hc811e2 9000 afff 8 kbytes rom/eprom * * 20 kbytes rom/eprom are contained in two segments of 8 kbytes and 12 kbytes each. ffc0 ffff normal modes interrupt vectors 64-byte register block 768 bytes ram single chip bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded d000 ffff bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom 12 kbytes rom/eprom * boot rom ext ext 02ff ext ext $9000 ext ext ext ffc0 ffff normal modes interrupt vectors 64-byte register block 256 bytes ram single chip bootstrap special test ext $0000 $1000 $f800 $ffff 0000 1000 103f bf00 expanded f800 ffff bfff bfc0 bfff special modes interrupt vectors 2048 bytes eeprom boot rom ext ext 00ff ext
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 34 freescale semiconductor addr. register name bit 7 6 5 4 3 2 1 bit 0 $1000 port a data register (porta) see page 98. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: i 0 0 0 i i i i $1001 reserved r r r r r r r r $1002 parallel i/o control register (pioc) see page 102. read: staf stai cwom hnds oin pls ega invb write: reset: 0 0 0 0 0 u 1 1 $1003 port c data register (portc) see page 99. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: indeterminate after reset $1004 port b data register (portb) see page 99. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: 0 0 0 0 0 0 0 0 $1005 port c latched register (portcl) see page 99. read: pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 write: reset: indeterminate after reset $1006 reserved r r r r r r r r $1007 port c data direction register (ddrc) see page 100. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $1008 port d data register (portd) see page 100. read: 0 0 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: u u i i i i i i $1009 port d data direction register (ddrd) see page 100. read: ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 0 0 0 0 0 0 0 0 $100a port e data register (porte) see page 101. read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: indeterminate after reset $100b timer compare force register (cforc) see page 135. read: foc1 foc2 foc3 foc4 foc5 write: reset: 0 0 0 0 0 0 0 0 $100c output compare 1 mask register (oc1m) see page 136. read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset: 0 0 0 0 0 0 0 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 1 of 6)
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 35 $100d output compare 1 data register (oc1d) see page 136. read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset: 0 0 0 0 0 0 0 0 $100e timer counter register high (tcnth) see page 137. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $100f timer counter register low (tcntl) see page 137. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $1010 timer input capture 1 register high (tic1h) see page 132. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1011 timer input capture 1 register low (tic1l) see page 132. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1012 timer input capture 2 register high (tic2h) see page 132. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1013 timer input capture 2 register low (tic2l) see page 132. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1014 timer input capture 3 register high (tic3h) see page 132. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1015 timer input capture 3 register low (tic3l) see page 132. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1016 timer output compare 1 register high (toc1h) see page 134. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11 1 1 1 1 11 $1017 timer output compare 1 register low (toc1l) see page 134. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11 1 1 1 1 11 $1018 timer output compare 2 register high (toc2h) see page 134. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11 1 1 1 1 11 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 2 of 6)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 36 freescale semiconductor $1019 timer output compare 2 register low (toc2l) see page 134. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11 1 1 1 1 11 $101a timer output compare 3 register high (toc3h) see page 135. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11 1 1 1 1 11 $101b timer output compare 3 register low (toc3l) see page 135. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11 1 1 1 1 11 $101c timer output compare 4 register high (toc4h) see page 135. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11 1 1 1 1 11 $101d timer output compare 4 register low (toc4l) see page 135. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11 1 1 1 1 11 $101e timer input capture 4/output compare 5 register high (ti4/o5) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11 1 1 1 1 11 $101f timer input capture 4/output compare 5 register low (ti4/o5) see page 133. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11 1 1 1 1 11 $1020 timer control register 1 (tctl1) see page 137. read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset: 0 0 0 0 0 0 0 0 $1021 timer control register 2 (tctl2) see page 131. read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset: 0 0 0 0 0 0 0 0 $1022 timer interrupt mask 1 register (tmsk1) see page 138. read: oc1i oc2i oc3i oc4i i4 /o5i ic1i ic2i ic3i write: reset: 0 0 0 0 0 0 0 0 $1023 timer interrupt flag 1 (tflg1) see page 138. read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset: 0 0 0 0 0 0 0 0 $1024 timer interrupt mask 2 register (tmsk2) see page 139. read: toi rtii paovi paii pr1 pr0 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 3 of 6)
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 37 $1025 timer interrupt flag 2 (tflg2) see page 142. read: tof rtif paovf paif write: reset: 0 0 0 0 0 0 0 0 $1026 pulse accumulator control regis- ter (pactl) see page 142. read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset: 0 0 0 0 0 0 0 0 $1027 pulse accumulator count regis- ter (pacnt) see page 146. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1028 serial peripheral control register (spcr) see page 123. read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset: 0 0 0 0 0 1 u u $1029 serial peripheral status register (spsr) see page 124. read: spif wcol modf write: reset: 0 0 0 0 0 0 0 0 $102a serial peripheral data i/o regis- ter (spdr) see page 125. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $102b baud rate register (baud) see page 113. read: tclr scp2 (1) scp1 scp0 rckb scr2 scr1 scr0 write: reset: 0 0 0 0 0 u u u $102c serial communications control register 1 (sccr1) see page 110. read: r8 t8 m wake write: reset: i i 0 0 0 0 0 0 $102d serial communications control register 2 (sccr2) see page 111. read: tie tcie rie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $102e serial communications status register (scsr) see page 112. read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 0 1. scp2 adds 39 to sci prescaler and is present only in mc68hc(7)11e20. $102f serial communications data reg- ister (scdr) see page 110. read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: indeterminate after reset $1030 analog-to-digital control status register (adctl) see page 62. read: ccf scan mult cd cc cb ca write: reset: 0 0 indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 4 of 6)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 38 freescale semiconductor $1031 analog-to-digital results register 1 (adr1) see page 64. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1032 analog-to-digital results register 2 (adr2) see page 64. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1033 analog-to-digital results register 3 (adr3) see page 64. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1034 analog-to-digital results register 4 (adr4) see page 64. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1035 block protect register (bprot) see page 52. read: ptcon bprt3 bprt2 bprt1 bprt0 write: reset: 0 0 0 1 1 1 1 1 $1036 eprom programming control register (eprog) (1 ) see page 53. read: mbe elat excol exrow t1 t0 pgm write: reset: 0 0 0 0 0 0 0 0 $1037 reserved r r r r r r r r 1. mc68hc711e20 only $1038 reserved r r r r r r r r $1039 system configuration options register (option) see page 46. read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset: 0 0 0 1 0 0 0 0 $103a arm/reset cop timer circuitry register (coprst) see page 81. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $103b eprom and eeprom program- ming control register (pprog) see page 49. read: odd even elat (2) byte row erase eelat epgm write: reset: 0 0 0 0 0 0 0 0 $103c highest priority i bit interrupt and miscellaneous register (hprio) see page 41. read: rboot smod mda irv(ne) psel3 psel2 psel1 psel0 write: reset: 0 0 0 0 0 1 1 0 $103d ram and i/o mapping register (init) see page 45. read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset: 0 0 0 0 0 0 0 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 5 of 6)
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 39 2.3.1 ram and i nput/output mapping hardware priority is built into ram and i/o mappi ng. registers have priority over ram and ram has priority over rom. when a lower priority resource is mapped at the same location as a higher priority resource, a read/write of a location results in a read/wri te of the higher priority resource only. for example, if both the register block and the ram are mapped to the same location, only the register block will be accessed. if ram and rom are located at the same position, ram has priority. the fully static ram can be used to store instructions, variables, and temporary data. the direct addressing mode can access ram locations using a 1-byte address operand, saving program memory space and execution time, depending on the application. ram contents can be preserved dur ing periods of processor inactivi ty by two methods, both of which reduce power consumption. they are: 1. in the software-based stop mode, the clocks are stopped while v dd powers the mcu. because power supply current is directly related to oper ating frequency in cmos integrated circuits, only a very small amount of leakage exis ts when the clocks are stopped. 2. in the second method, the modb/v stby pin can supply ram power from a battery backup or from a second power supply. figure 2-8 shows a typical standby voltage circuit for a standard 5-volt device. adjustments to the circuit must be made for devices that operate at lower voltages. using the modb/v stby pin may require external hardware, but c an be justified when a significant amount of external circuitry is operating from v dd . if v stby is used to maintain ram contents, reset must be held low whenever v dd is below normal operating level. refer to chapter 5 resets and interrupts . $103e reserved r r r r r r r r $103f system configuration register (config) see page 43. read: nosec nocop romon eeon write: reset: 0 0 0 0 u u 1 u $103f system configuration register (config) (3) see page 43. read: ee3 ee2 ee1 ee0 nosec nocop eeon write: reset: 1 1 1 1 u u 1 1 1. can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. 2. mc68hc711e9 only 3. mc68hc811e2 only addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 2-7. register and control bit assignments (sheet 6 of 6)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 40 freescale semiconductor figure 2-8. ram standby modb/v stby connections the bootloader program is contained in the internal b ootstrap rom. this rom, which appears as internal memory space at locations $bf00?$bfff, is enabled only if the mcu is reset in special bootstrap mode. in expanded modes, the rom/eprom/otprom (if present ) is enabled out of reset and located at the top of the memory map if the romon bit in the conf ig register is set. rom or eprom is enabled out of reset in single-chip and bootstrap modes, regardless of the state of romon. for devices with 512 bytes of eeprom, the eeprom is located at $b600?$b7ff and has the same read cycle time as the internal rom. the 512 bytes of eeprom cannot be rema pped to other locations. for the mc68hc811e2, eeprom is located at $f800?$ffff and can be rema pped to any 4-kbyte boundary. eeprom mapping control bits (ee[3:0] in config) determine the location of the 2048 bytes of eeprom and are present only on the mc68hc811e2. refer to 2.3.3.1 system configuration register for a description of the mc68hc811e2 config register. eeprom can be programmed or erased by software and an on-chip charge pump, allowing eeprom changes using the single v dd supply. 2.3.2 mode selection the four mode variations are selected by the logic states of the moda and modb pins during reset. the moda and modb logic levels determine the logic state of smod and the mda control bits in the highest priority i-bit interrupt and miscellaneous (hprio) register. after reset is released, the mode select pins no longer influence the mcu operating mode. in single-chip operating mode, the moda pin is connected to a logic level 0. in expanded mode, moda is normally connected to v dd through a pullup resistor of 4.7 k ? . the moda pin also functi ons as the load instruction register lir pin when the mcu is not in reset. the open-drain active low lir output pin drives low during the first e cycle of each instruction. the mo db pin also functions as standby power input (v stby ), which allows ram contents to be maintained in absence of v dd . refer to table 2-1 , which is a summary of mode pin operation, the mode control bits, and the four operating modes. 4.7 k max 690 v batt + 4.8-v nicd v dd v dd v out to modb/v stby of m68hc11
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 41 a normal mode is selected when modb is logic 1 duri ng reset. one of three reset vectors is fetched from address $fffa?$ffff, and program execution begins from the address indicated by this vector. if modb is logic 0 during reset, the special mode rese t vector is fetched from addresses $bffa?$bfff, and software has access to special test features. refer to chapter 5 resets and interrupts . rboot ? read bootstrap rom bit valid only when smod is set (bootstrap or specia l test mode); can be written only in special modes 0 = bootloader rom disabled and not in map 1 = bootloader rom enabled and in map at $be00?$bfff smod and mda ? special mode select and mode select a bits the initial value of smod is the inverse of the logi c level present on the modb pin at the rising edge of reset. the initial value of mda equals the logic level present on the moda pin at the rising edge of reset. these two bits can be read at any time. they can be written anytime in special modes. mda can be written only once in normal modes. sm od cannot be set once it has been cleared. table 2-1. hardware mode select summary input levels at reset mode control bits in hprio (latched at reset) modb moda rboot smod mda 1 0 single chip 0 0 0 1 1 expanded 0 0 1 00bootstrap110 01special test011 address: $103c bit 7 6 5 4 3 2 1 bit 0 read: rboot (1) smod (1) mda (1) irv(ne) (1) psel3 psel2 psel1 psel0 write: resets: single chip:000 0 0110 expanded:001 0 0110 bootstrap:110 0 0110 test:011 1 0110 1. the reset values depend on the mode selected at the reset pin rising edge. figure 2-9. highest priority i-bit interrupt and miscellaneous register (hprio) input mode latched at reset modb moda smod mda 1 0 single chip 0 0 1 1 expanded 0 1
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 42 freescale semiconductor irv(ne) ? internal read visibility (not e) bit irvne can be written once in any mode. in expand ed modes, irvne determines whether irv is on or off. in special test mode, irvne is reset to 1. in all other modes, irvne is reset to 0. for the mc68hc811e2, this bit is irv and only controls the internal read visibility function. 0 = no internal read visibility on external bus 1 = data from internal reads is driven out the external data bus. in single-chip modes this bit determines whether the e clock drives out from the chip. for the mc68hc811e2, this bit has no meaning or effect in single-chip and bootstrap modes. 0 = e is driven out from the chip. 1 = e pin is driven low. refer to the following table. psel[3:0] ? priority select bits refer to chapter 5 resets and interrupts . 2.3.3 system initialization registers and bits that control initialization and the basic operation of the mcu are protected against writes except under special circumstances. table 2-2 lists registers that can be written only once after reset or that must be written within the first 64 cycles after reset. 0 0 bootstrap 1 0 0 1 special test 1 1 mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne can be written single chip 0 on off e once expanded 0 on off irv once bootstrap 0 on off e once special test 1 on on irv once table 2-2. write access limited registers operating mode register address register name must be written in first 64 cycles write anytime smod = 0 $x024 timer interrupt mask 2 (t msk2) bits [1:0], once only bits [7:2] $x035 block protect register (bprot) clear bits, once only set bits only $x039 system configuration options (option) bits [5:4], bits [2:0], once only bits [7:6], bit 3 $x03c highest priority i-bit interrupt and miscellaneous (hprio) see hprio description see hprio description $x03d ram and i/o map register (init) yes, once only ? smod = 1 $x024 timer interrupt ma sk 2 (tmsk2) ? all, set or clear $x035 block protect register (bprot) ? all, set or clear $x039 system configuration options (option) ? all, set or clear $x03c highest priority i-bit interrupt and miscellaneous (hprio) see hprio description see hprio description $x03d ram and i/o map register (init) ? all, set or clear
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 43 2.3.3.1 system configuration register the system configuration register (config) consists of an eeprom byte and static latches that control the startup configuration of the mcu. the contents of the eeprom byte are transferred into static working latches during reset sequences. the operation of the mcu is controlled directly by these latches and not by config itself. in norm al modes, changes to config do not affect operation of the mcu until after the next reset sequence. when programming, the config register itself is accessed. when the config register is read, the st atic latches are accessed. see 2.5.1 eeprom and config programming and erasure for information on modifying config. to take full advantage of the mcu?s functionality, customers can program the config register in bootstrap mode. this can be accomplished by setti ng the mode pins to logic 0 and downloading a small program to internal ram. for more information, freescale application note an1060 entitled m68hc11 bootstrap mode has been included at the back of this docum ent. the downloadable talk er will consist of: bulk erase byte programming communication server all of this functionality is provided by pcbug11 which can be found on the freescale web site at http://www.freescale.com . for more information on using pcbug11 to program an e-series device, freescale engineering bulletin eb296 entitled programming mc68hc711e9 devices with pcbug11 and the m68hc11evbu has been included at the back of this document. note the config register on the 68hc11 is an eeprom cell and must be programmed accordingly. operation of the config register in the mc68hc81 1e2 differs from other devices in the m68hc11 e series. see figure 2-10 and figure 2-11 . address: $103f bit 7654321bit 0 read: nosec nocop romon eeon write: resets: single chip: bootstrap: expanded: test: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u 1 1 u u(l) u u(l) 1 u u u u u u u = unimplemented u indicates a previously programmed bit. u(l) indicates that the bit resets to the logic level held in the latch prior to reset , but the function of cop is controlled by the disr bit in test1 register. figure 2-10. system configuration register (config)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 44 freescale semiconductor ee[3:0] ? eeprom mapping bits ee[3:0] apply only to mc68hc811e2 and allow the 2048 bytes of eeprom to be remapped to any 4-kbyte boundary. see table 2-3 . address: $103f bit 7654321bit 0 read: ee3 ee2 ee1 ee0 nosec nocop eeon write: resets: single chip: bootstrap: expanded: test: 1 1 u u 1 1 u u 1 1 u u 1 1 u u u u 1 1 u u(l) u u(l) 1 1 1 1 1 1 u 0 = unimplemented u indicates a previously programmed bit. u(l) indicates that the bit resets to the logic level held in the latch prior to reset , but the function of cop is controlled by the disr bit in test1 register. figure 2-11. mc68hc811e2 system configuration register (config) table 2-3. eeprom mapping ee[3:0] eeprom location 0 0 0 0 $0800?$0fff 0 0 0 1 $1800?$1fff 0 0 1 0 $2800?$2fff 0 0 1 1 $3800?$3fff 0 1 0 0 $4800?$4fff 0 1 0 1 $5800?$5fff 0 1 1 0 $6800?$6fff 0 1 1 1 $7800?$7fff 1 0 0 0 $8800?$8fff 1 0 0 1 $9800?$9fff 1 0 1 0 $a800?$afff 1 0 1 1 $b800?$bfff 1 1 0 0 $c800?$cfff 1 1 0 1 $d800?$dfff 1 1 1 0 $e800?$efff 1 1 1 1 $f800?$ffff
memory map m68hc11e family data sheet, rev. 5.1 freescale semiconductor 45 nosec ? security disable bit nosec is invalid unless the security mask option is specified before the mcu is manufactured. if the security mask option is omitted nosec always read s 1. the enhanced security feature is available in the mc68s711e9 mcu. the enhancement to the standa rd security feature protects the eprom as well as ram and eeprom. 0 = security enabled 1 = security disabled nocop ? cop system disable bit refer to chapter 5 resets and interrupts . 1 = cop disabled 0 = cop enabled romon ? rom/eprom/otprom enable bit when this bit is 0, the rom or eprom is disabled and that memory space becomes externally addressed. in single-chip mode, romon is forced to 1 to enable rom/eprom regardless of the state of the romon bit. 0 = rom disabled from the memory map 1 = rom present in the memory map eeon ? eeprom enable bit when this bit is 0, the eeprom is disabled and that memory space becomes externally addressed. 0 = eeprom removed from the memory map 1 = eeprom present in the memory map 2.3.3.2 ram and i/o mapping register the internal registers used to control the operation of the mcu can be relocated on 4-kbyte boundaries within the memory space with the use of the ra m and i/o mapping register (init). this 8-bit special-purpose register can chang e the default locations of the ram and control registers within the mcu memory map. it can be written only once within th e first 64 e-clock cycles after a reset in normal modes, and then it becomes a read-only register. ram[3:0] ? ram map position bits these four bits, which specify the upper hexadecimal digit of the ram address, control position of ram in the memory map. ram can be positioned at the be ginning of any 4-kbyte page in the memory map. it is initialized to address $0000 out of reset. refer to table 2-4 . reg[3:0] ? 64-byte register block position these four bits specify the upper hexadecimal digit of the address fo r the 64-byte block of internal registers. the register block, positioned at the begi nning of any 4-kbyte page in the memory map, is initialized to address $1000 out of reset. refer to table 2-5 . address: $103d bit 7654321bit 0 read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset: 00000001 figure 2-12. ram and i/o mapping register (init)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 46 freescale semiconductor 2.3.3.3 system configuration options register the 8-bit, special-purpose system configuration opti ons register (option) sets internal system configuration options during initialization. the time protected control bits, irqe, dly, and cr[1:0], can be written only once after a reset and then they become read-only. this minimizes the possibility of any accidental changes to the system configuration. adpu ? analog-to-digital converter power-up bit refer to chapter 3 analog-to-digital (a/d) converter . csel ? clock select bit selects alternate clock source for on -chip eeprom charge pump. refer to 2.5.1 eeprom and config programming and erasure for more information on eeprom use. csel also selects the clock source for t he a/d converter, a function discussed in chapter 3 analog-to-digital (a/d) converter . table 2-4. ram mapping table 2-5. register mapping ram[3:0] address reg[3:0] address 0000 $0000?$0xff 0000 $0000?$003f 0001 $1000?$1xff 0001 $1000?$103f 0010 $2000?$2xff 0010 $2000?$203f 0011 $3000?$3xff 0011 $3000?$303f 0100 $4000?$4xff 0100 $4000?$403f 0101 $5000?$5xff 0101 $5000?$503f 0110 $6000?$6xff 0110 $6000?$603f 0111 $7000?$7xff 0111 $7000?$703f 1000 $8000?$8xff 1000 $8000?$803f 1001 $9000?$9xff 1001 $9000?$903f 1010 $a000?$axff 1010 $a000?$a03f 1011 $b000?$bxff 1011 $b000?$b03f 1100 $c000?$cxff 1100 $c000?$c03f 1101 $d000?$dxff 1101 $d000?$d03f 1110 $e000?$exff 1110 $e000?$e03f 1111 $f000?$fxff 1111 $f000?$f03f address: $1039 bit 7654321bit 0 read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset: 00010000 1. can be written only once in fi rst 64 cycles out of reset in norm al modes or at any time during special modes. = unimplemented figure 2-13. system configuration options register (option)
eprom/otprom m68hc11e family data sheet, rev. 5.1 freescale semiconductor 47 irqe ? configure irq for edge-sensitive only operation bit refer to chapter 5 resets and interrupts . dly ? enable oscillator startup delay bit 0 = the oscillator startup delay coming out of stop mode is bypassed and the mcu resumes processing within about four bus cycles. 1 = a delay of approximately 4000 e- clock cycles is imposed as the mcu is started up from the stop power-saving mode. this delay allows the crystal oscillator to stabilize. cme ? clock monitor enable bit refer to chapter 5 resets and interrupts . bit 2 ? not implemented always reads 0 cr[1:0] ? cop timer rate select bits the internal e clock is divided by 2 15 before it enters the cop watchdog system. these control bits determine a scaling factor for the watchdog timer. refer to chapter 5 resets and interrupts . 2.4 eprom/otprom certain devices in the m68hc11 e series include on-chip eprom/otprom. for instance: the mc68hc711e9 devices contain 12 kbytes of on-chip eprom (otprom in non-windowed package). the mc68hc711e20 has 20 kbytes of eprom (otprom in non-windowed package). the mc68hc711e32 has 32 kbytes of eprom (otprom in non-windowed package). standard mc68hc71e9 and mc68hc711e20 devices are shipped with the eprom/otprom contents erased (all 1s). the programming operation programs zeros. windowed devices must be erased using a suitable ultraviolet light source before reprogram ming. depending on the light source, erasing can take from 15 to 45 minutes. using the on-chip eprom/otprom programming featur e requires an external 12-volt nominal power supply (v ppe ). normal programming is accomplished us ing the eprom/otprom programming register (pprog). pprog is the combined eprom/ otprom and eeprom programming register on all devices with eprom/otprom except the mc68hc711e20. for the mc 68hc711e20, there is a separate register for eprom/otprom programming called the eprog register. as described in the following subsections, these tw o methods of programming and verifying eprom are possible: 1. programming an individual eprom address 2. programming the eprom with downloaded data
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 48 freescale semiconductor 2.4.1 programming an i ndividual epro m address in this method, the mcu programs its own eprom by controlling the pprog register (eprog in mc68hc711e20). use these procedures to program the eprom through the mcu with: the romon bit set in the config register the 12-volt nominal programming voltage present on the xirq /v ppe pin the irq pin must be pulled high. note any operating mode can be used. this example applies to all devices with eprom/otprom except for the mc68hc711e20. eprog ldab #$20 stab $103b set elat bit in (epgm = 0) to enable eprom latches. staa $0,x store data to eprom address ldab #$21 stab $103b set epgm bit with elat = 1 to enable eprom programming voltage jsr dlyep delay 2?4 ms clr $103b turn off programming voltage and set to read mode this example applies only to mc68hc711e20. eprog ldab #$20 stab $1036 set elat bit (epgm = 0) to enable eprom latches. staa $0,x store data to eprom address ldab #$21 stab $1036 set epgm bit with elat = 1 to enable eprom programming voltage jsr dlyep delay 2?4 ms clr $1036 turn off programming voltage and set to read mode 2.4.2 programming the ep rom with downloaded data when using this method, the eprom is programmed by software while in the special test or bootstrap modes. user-developed software can be uploaded th rough the sci or a rom-resident eprom programming utility can be used. the 12-volt no minal programming voltage must be present on the xirq /v ppe pin. to use the resident utility, bootload a 3-byte program consisting of a single jump instruction to $bf00. $bf00 is the starting address of a resident eprom programming utility. the utility program sets the x and y index registers to default values, then receives programming data from an external host, and puts it in eprom. the value in ix determines programming delay time. the value in iy is a pointer to the first address in eprom to be programmed (default = $d000). when the utility program is ready to receive program ming data, it sends the host the $ff character. then it waits. when the host sees the $ff character, the eprom programming data is sent, starting with the first location in the eprom array. after the last byte to be programmed is sent and the corresponding verification data is returned, the programming op eration is terminated by resetting the mcu. for more information, freescal e application note an1060 entitled m68hc11 bootstrap mode has been included at the back of this document.
eprom/otprom m68hc11e family data sheet, rev. 5.1 freescale semiconductor 49 2.4.3 eprom and ee prom programming co ntrol register the eprom and eeprom programming control regist er (pprog) enables t he eprom programming voltage and controls the latching of data to be programmed. for mc68hc711e9, pprog is also t he eeprom programming control register. for the mc68hc711e20, eprom programming is controlled by the eprog register and eeprom programming is controlled by the pprog register. odd ? program odd rows in half of eeprom (test) bit refer to 2.5 eeprom . even ? program even rows in half of eeprom (test) bit refer to 2.5 eeprom . elat ? eprom/otprom latch control bit when elat = 1, writes to eprom cause address and data to be latched and the eprom/otprom cannot be read. elat can be read any time. elat can be written any time except when epgm = 1; then the write to elat is disabled. 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming for the mc68hc711e9: a. epgm enables the high voltage necess ary for both eeprom and eprom/otprom programming. b. elat and eelat are mutually exclusive and cannot both equal 1. byte ? byte/other eeprom erase mode bit refer to 2.5 eeprom . row ? row/all eeprom erase mode bit refer to 2.5 eeprom . erase ? erase mode select bit refer to 2.5 eeprom . eelat ? eeprom latch control bit refer to 2.5 eeprom . epgm ?eprom/otprom/eeprom progr amming voltage enable bit epgm can be read any time and can be written only when elat = 1 (for eprom/otprom programming) or when eelat = 1 (for eeprom programming). 0 = programming voltage to eprom /otprom/eeprom array disconnected 1 = programming voltage to eprom /otprom/eeprom array connected address: $103b bit 7654321bit 0 read: odd even elat (1) byte row erase eelat epgm write: reset: 00000000 1. mc68hc711e9 only figure 2-14. eprom and eeprom programming control register (pprog)
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 50 freescale semiconductor mbe ? multiple-byte programming enable bit when multiple-byte programming is enabled, address bit 5 is considered a don?t care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get programmed. mbe can be read in any mode and always reads 0 in normal modes. mbe can be written only in special modes. 0 = eprom array configured for normal programming 1 = program two bytes with the same data bit 6 ? unimplemented always reads 0 elat ? eprom/otprom latch control bit when elat = 1, writes to eprom cause address and data to be latched and the eprom/otprom cannot be read. elat can be read any time. elat can be written any time except when pgm = 1; then the write to elat is disabled. 0 = eprom/otprom address and data bus configured for normal reads 1 = eprom/otprom address and data bus configured for programming excol ? select extra columns bit 0 = user array selected 1 = user array is disabled and extra columns are ac cessed at bits [7:0]. addresses use bits [13:5] and bits [4:0] are don?t care. excol can be read and written only in special modes and always returns 0 in normal modes. exrow ? select extra rows bit 0 = user array selected 1 = user array is disabled and two extra rows are av ailable. addresses use bits [7:0] and bits [13:8] are don?t care. exrow can be read and written only in special modes and always returns 0 in normal modes. t[1:0] ? eprom test mode select bits these bits allow selection of either gate stress or drain stress test modes. they can be read and written only in special modes and always read 0 in normal modes. address: $1036 bit 7654321bit 0 read: mbe elat excol exrow t1 t0 pgm write: reset: 00000000 = unimplemented figure 2-15. mc68hc711e20 eprom programming control register (eprog) t1 t0 function selected 0 0 normal mode 01 reserved 1 0 gate stress 1 1 drain stress
eeprom m68hc11e family data sheet, rev. 5.1 freescale semiconductor 51 pgm ? eprom programming voltage enable bit pgm can be read any time and can be written only when elat = 1. 0 = programming voltage to eprom array disconnected 1 = programming voltage to eprom array connected 2.5 eeprom some e-series devices contain 512 bytes of on -chip eeprom. the mc68hc81 1e2 contains 2048 bytes of eeprom with selectable base address. all e-series devices contain the eeprom-based config register. 2.5.1 eeprom and config programming and erasure the erased state of an eeprom bit is 1. during a r ead operation, bit lines ar e precharged to 1. the floating gate devices of programmed bits conduct and pu ll the bit lines to 0. unprogrammed bits remain at the precharged level and are read as ones. progra mming a bit to 1 causes no change. programming a bit to 0 changes the bit so that subsequent reads return 0. when appropriate bits in the bprot register are cl eared, the pprog register controls programming and erasing the eeprom. the pprog register can be read or written at any time, but logic enforces defined programming and erasing sequences to prevent unintentional changes to eeprom data. when the eelat bit in the pprog register is cleared, th e eeprom can be read as if it were a rom. the on-chip charge pump that generates the eeprom programmi ng voltage from v dd uses mos capacitors, which are relatively small in value. the e fficiency of this charge pump and its drive capability are affected by the level of v dd and the frequency of the driving clock. the load depends on the number of bits being programmed or erased and capacitances in the eeprom array. the clock source driving the charge pump is software selectable. when the clock select (csel) bit in the option register is 0, the e clock is used; when c sel is 1, an on-chip resistor-capacitor (rc) oscillator is used. the eeprom programmi ng voltage power supply voltage to the eeprom array is not enabled until there has been a write to pprog with eelat set and pgm cleared. this must be followed by a write to a valid eeprom location or to the config address, and then a write to pprog with both the eelat and epgm bits set. any attempt to set both eelat and epgm during the same write operation results in neither bit being set. 2.5.1.1 block protect register this register prevents inadvertent writes to both the config register and eepr om. the active bits in this register are initialized to 1 out of reset and ca n be cleared only during the first 64 e-clock cycles after reset in the normal modes. when these bits ar e cleared, the associated eeprom section and the config register can be programmed or erased. eepr om is only visible if the eeon bit in the config register is set. the bits in the bprot register can be written to 1 at any time to protect eeprom and the config register. in test or bootstrap modes, writ e protection is inhibited and bprot can be written repeatedly. address ranges for protected areas of eeprom differ significantly for the mc68hc811e2. refer to figure 2-16 .
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 52 freescale semiconductor bits [7:5] ? unimplemented always read 0 ptcon ? protect config register bit 0 = config register can be pr ogrammed or erased normally. 1 = config register cannot be programmed or erased. bprt[3:0] ? block protect bits for eeprom when set, these bits protect a block of eeprom fr om being programmed or electronically erased. ultraviolet light, however, can erase the entire eeprom contents regardless of bprt[3:0] (windowed packages only). refer to table 2-6 and table 2-7 . when cleared, bprt[3:0] allow programmin g and erasure of the associated block. address: $1035 bit 7654321bit 0 read: ptcon bprt3 bprt2 bprt1 bprt0 write: reset: 00011111 = unimplemented figure 2-16. block protect register (bprot) table 2-6. eeprom block protect bit name block protected block size bprt0 $b600?$b61f 32 bytes bprt1 $b620?$b65f 64 bytes bprt2 $b660?$b6df 128 bytes bprt3 $b6e0?$b7ff 288 bytes table 2-7. eeprom block protect in mc68hc811e2 mcus bit name block protected block size bprt0 $x800?$x9ff (1) 1. x is determined by the value of ee[ 3:0] in config register. refer to figure 2-13 . 512 bytes bprt1 $xa00?$xbff (1) 512 bytes bprt2 $xc00?$xdff (1) 512 bytes bprt3 $xe00?$xfff (1) 512 bytes
eeprom m68hc11e family data sheet, rev. 5.1 freescale semiconductor 53 2.5.1.2 eprom and eeprom programming control register the eprom and eeprom programming control register (pprog) selects and controls the eeprom programming function. bits in pprog enable the progr amming voltage, control the latching of data to be programmed, and select the method of erasure (for example, byte, row, etc.). odd ? program odd rows in half of eeprom (test) bit even ? program even rows in half of eeprom (test) bit elat ? eprom/otprom latch control bit for the mc68hc711e9, epgm enables the high voltage necessary for both eprom/otprom and eeprom programming. for mc68hc711e9, elat and eelat are mutually exclusive and cannot both equal 1. 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming byte ? byte/other eeprom erase mode bit this bit overrides the row bit. 0 = row or bulk erase 1 = erase only one byte row ? row/all eeprom erase mode bit if byte is 1, row has no meaning. 0 = bulk erase 1 = row erase erase ? erase mode select bit 0 = normal read or program mode 1 = erase mode eelat ? eeprom latch control bit 0 = eeprom address and data bus configured for normal reads and cannot be programmed 1 = eeprom address and data bus configured fo r programming or erasing and cannot be read address: $103b bit 7654321bit 0 read: odd even elat (1) byte row erase eelat epgm write: reset: 0 0000000 1. mc68hc711e9 only figure 2-17. eprom and eeprom programming control register (pprog) table 2-8. eeprom erase byte row action 0 0 bulk erase (entire array) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 54 freescale semiconductor epgm ? eprom/otprom/eeprom programming voltage enable bit 0 = programming voltage to eeprom array switched off 1 = programming voltage to eeprom array switched on during eeprom programming, the row and byte bits of pprog are no t used. if the frequency of the e clock is 1 mhz or less, set the csel bit in the op tion register. recall that 0s must be erased by a separate erase operation before programming. the fo llowing examples of how to program an eeprom byte assume that the appropriate bits in bprot are cleared. prog ldab #$02 eelat = 1 stab $103b set eelat bit staa $xxxx store data to eeprom address (for valid eeprom address see memory map for each device) ldab #$03 eelat = 1, epgm = 1 stab $103b turn on programming voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 2.5.1.3 eeprom bulk erase this is an example of how to bulk erase the entire eeprom. the config register is not affected in this example. bulke ldab #$06 eelat = 1, erase = 1 stab $103b set to bulk erase mode staa $xxxx store data to any eeprom address (for valid eeprom address see memory map for each device) ldab #$07 eelat = 1, epgm = 1, erase = 1 stab $103b turn on high voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 2.5.1.4 eeprom row erase this example shows how to perform a fa st erase of large sections of eeprom. rowe ldab #$0e row = 1, erase = 1, eelat = 1 stab $103b set to row erase mode stab 0,x write any data to any address in row ldab #$0f row = 1, erase = 1, eelat = 1, epgm = 1 stab $103b turn on high voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode
eeprom m68hc11e family data sheet, rev. 5.1 freescale semiconductor 55 2.5.1.5 eeprom byte erase this is an example of how to erase a single byte of eeprom. bytee ldab #$16 byte = 1, erase = 1, eelat = 1 stab $103b set to byte erase mode stab 0,x write any data to address to be erased ldab #$17 byte = 1, erase = 1, eelat = 1, epgm = 1 stab $103b turn on high voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 2.5.1.6 config register programming because the config register is implemented with eeprom cells, use eeprom procedures to erase and program this register. the procedure for programming is the same as for programming a byte in the eeprom array, except that the config register address is used. config can be programmed or erased (including byte erase) while the mcu is ope rating in any mode, provided that ptcon in bprot is clear. to change the value in the config register, complete this procedure. 1. erase the config register. 2. program the new value to the config address. 3. initiate reset. note do not initiate a reset until the procedure is complete. 2.5.2 eeprom security the optional security feature, available only on rom-based mcus , protects the eeprom and ram contents from unauthorized access. a program, or a key portion of a program, can be protected against unauthorized duplication. to accomplish this, the pr otection mechanism restricts operation of protected devices to the single-chip modes. this prevents th e memory locations from being monitored externally because single-chip modes do not al low visibility of the internal address and data buses. resident programs, however, have unlimited access to the in ternal eeprom and ram and can read, write, or transfer the contents of these memories. an enhanced security feature which protects epr om contents, ram, and eeprom from unauthorized accesses is available in mc68s711e9. refer to chapter 11 ordering information and mechanical specifications for the exact part number. for further information, these engineering bulleti ns have been included at the back of this data book: eb183 ? enabling the security feature on the mc68hc711e9 devices with pcbug11 on the m68hc711e9pgmr eb188 ? enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr
operating modes and on-chip memory m68hc11e family data sheet, rev. 5.1 56 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 57 chapter 3 analog-to-digital (a/d) converter 3.1 introduction the analog-to-digital (a/d) system, a successive appr oximation converter, uses an all-capacitive charge redistribution technique to convert analog signals to digital values. 3.2 overview the a/d system is an 8-channel, 8-bit, multiplexed- input converter. the converter does not require external sample and hold circuits because of the ty pe of charge redistribution technique used. a/d converter timing can be synchronized to the system e cl ock or to an internal resistor capacitor (rc) oscillator. the a/d converter system consists of four functional blocks: multiplexer, analog converter, digital control, and result storage. refer to figure 3-1 . 3.2.1 multiplexer the multiplexer selects one of 16 inputs for conversion. input selection is controlled by the value of bits cd:ca in the adctl register. the eight port e pins are fixed-direction analog inputs to the multiplexer, and additional internal analog si gnal lines are routed to it. port e pins also can be used as digital inputs. di gital reads of port e pins are not recommended during the sample portion of an a/d conversion cycle, when the gate signal to the n-channel input gate is on. because no p-channel devices are dire ctly connected to either input pins or reference voltage pins, voltages above v dd do not cause a latchup problem, although current should be limited according to maximum ratings. refer to figure 3-2 , which is a functional diagram of an input pin. 3.2.2 analog converter conversion of an analog input selected by the mult iplexer occurs in this block. it contains a digital-to-analog capacitor (dac) array, a comparat or, and a successive approximation register (sar). each conversion is a sequence of eight comparison op erations, beginning with th e most significant bit (msb). each comparison determines the value of a bit in the successive approximation register. the dac array performs two functions. it acts as a sample and hold circuit during the entire conversion sequence and provides comparison voltage to t he comparator during each successive comparison. the result of each successive comparison is stored in the sar. when a conversion sequence is complete, the contents of the sar are transferred to the appropriate result register. a charge pump provides switching voltage to the gat es of analog switches in the multiplexer. charge pump output must stabilize between 7 and 8 volts within up to 100 s before the converter can be used. the charge pump is enabled by the adpu bit in the option register.
analog-to-digital (a/d) converter m68hc11e family data sheet, rev. 5.1 58 freescale semiconductor figure 3-1. a/d converter block diagram figure 3-2. electrical model of an a/d input pin (sample mode) 8-bit capacitive dac with sample and hold successive approximation register and control result pe0 an0 pe1 an1 pe2 an2 pe3 an3 pe4 an4 pe5 an5 pe6 an6 pe7 an7 analog mux v rh v rl adctl a/d control ccf scan mult cd cc cb ca internal data bus adr1 a/d result 1 adr2 a/d result 2 adr3 a/d result 3 adr4 a/d result 4 result register interface diffusion/poly < 2 pf coupler 400 na junction leakage + ~20 v ? ~0.7 v * * this analog switch is closed only during the 12-cycle sample time. v rl input + ~12v ? ~0.7v protection device e 4 k ? dummy n-channel output device analog input pin ~ 20 pf dac capacitance
overview m68hc11e family data sheet, rev. 5.1 freescale semiconductor 59 3.2.3 digital control all a/d converter operations are controlled by bits in register adctl. in addition to selecting the analog input to be converted, adctl bits indicate conversion status and cont rol whether single or continuous conversions are performed. finally, the adctl bits determine whether conversions are performed on single or multiple channels. 3.2.4 result registers four 8-bit registers adr[4:1] store conversion resu lts. each of these registers can be accessed by the processor in the cpu. the conversion complete flag (ccf) indicates when valid data is present in the result registers. the result registers are written dur ing a portion of the system clock cycle when reads do not occur, so there is no conflict. 3.2.5 a/d converter clocks the csel bit in the option register selects whether the a/d converter uses the system e clock or an internal rc oscillator for sync hronization. when e-clock frequency is below 750 khz, charge leakage in the capacitor array can cause errors, and the inter nal oscillator should be used. when the rc clock is used, additional errors can occur because the comparator is sensitiv e to the additional system clock noise. 3.2.6 conversion sequence a/d converter operations are performed in sequences of four conversions each. a conversion sequence can repeat continuously or stop after one iteration. the conversion complete flag (ccf) is set after the fourth conversion in a sequence to show the av ailability of data in the result registers. figure 3-3 shows the timing of a typical sequence. synchronizati on is referenced to the system e clock. figure 3-3. a/d conversion sequence 0 32 64 96 128 ? e cycles sample analog input successive approximation sequence msb 4 cycles bit 6 2 cyc bit 5 2 cyc bit 4 2 cyc bit 3 2 cyc bit 2 2 cyc bit 1 2 cyc lsb 2 cyc 2 cyc end repeat sequence, scan = 1 set cc flag convert first channel, update adr1 convert second channel, update adr2 convert third channel, update adr3 convert fourth channel, update adr4 12 e cycles write to adctl e clock
analog-to-digital (a/d) converter m68hc11e family data sheet, rev. 5.1 60 freescale semiconductor 3.3 a/d converter power-up and clock select bit 7 of the option register controls a/d conver ter power-up. clearing adpu removes power from and disables the a/d converter system . setting adpu enables the a/d converter system. stabilization of the analog bias voltages requires a delay of as much as 100 s after turning on the a/d converter. when the a/d converter system is operating with the mcu e clock, all switching and comparator operations are inherently synchronized to the main mcu clocks. this allows the comparator output to be sampled at relatively quiet times during mcu cloc k cycles. since the internal rc os cillator is asynchronous to the mcu clock, there is more error attributable to inte rnal system clock noise. a/ d converter accuracy is reduced slightly while the internal rc oscillator is being used (csel = 1). adpu ? a/d power-up bit 0 = a/d powered down 1 = a/d powered up csel ? clock select bit 0 = a/d and eeprom use system e clock. 1 = a/d and eeprom use internal rc clock. irqe ? configure irq for edge-sensitive only operation refer to chapter 5 resets and interrupts . dly ? enable oscillator startup delay bit 0 = the oscillator startup delay coming out of stop is bypassed and the mcu resumes processing within about four bus cycles. 1 = a delay of approximately 4000 e- clock cycles is imposed as the mcu is started up from the stop power-saving mode. this delay allows the crystal oscillator to stabilize. cme ? clock monitor enable bit refer to chapter 5 resets and interrupts . bit 2 ? not implemented always reads 0 cr[1:0] ? cop timer rate select bits refer to chapter 5 resets and interrupts and chapter 9 timing systems . address: $1039 bit 7654321bit 0 read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset:00010000 1. can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes = unimplemented figure 3-4. system configuration options register (option)
conversion process m68hc11e family data sheet, rev. 5.1 freescale semiconductor 61 3.4 conversion process the a/d conversion sequence begins one e-clock cycle after a write to the a/d control/status register, adctl. the bits in adctl select th e channel and the mode of conversion. an input voltage equal to v rl converts to $00 and an input voltage equal to v rh converts to $ff (full scale), with no overflow indication. for ratiometric conversions of this type, the source of each analog input should use v rh as the supply voltage and be referenced to v rl . 3.5 channel assignments the multiplexer allows the a/d converter to select one of 16 analog signals. eight of these channels correspond to port e input lines to the mcu, four of the channels are internal reference points or test functions, and four channels are reserved. refer to table 3-1 . 3.6 single-channel operation the two types of single-channel operation are: 1. when scan = 0, the single selected channel is c onverted four consecutive times. the first result is stored in a/d result register 1 (adr1), and the fourth result is stored in adr4. after the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the adctl register. 2. when scan = 1, conversions continue to be performed on the selected channel with the fifth conversion being stored in register adr1 (overw riting the first conversion result), the sixth conversion overwriting adr2, and so on. table 3-1. converter channel assignments channel number channel signal result in adrx if mult = 1 1 an0 adr1 2 an1 adr2 3 an2 adr3 4 an3 adr4 5 an4 adr1 6 an5 adr2 7 an6 adr3 8 an7 adr4 9 ? 12 reserved ? 13 v rh (1) 1. used for factory testing adr1 14 v rl (1) adr2 15 (v rh )/2 (1) adr3 16 reserved (1) adr4
analog-to-digital (a/d) converter m68hc11e family data sheet, rev. 5.1 62 freescale semiconductor 3.7 multiple-channel operation the two types of multiple-channel operation are: 1. when scan = 0, a selected group of four channels is converted one time each. the first result is stored in a/d result register 1 (adr1), and the fourth result is stored in adr4. after the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the adctl register. 2. when scan = 1, conversions continue to be performed on the selected group of channels with the fifth conversion being stored in register adr1 (repl acing the earlier conversion result for the first channel in the group), the sixth conv ersion overwriting adr2, and so on. 3.8 operation in stop and wait modes if a conversion sequence is in progress when either the stop or wait mode is entered, the conversion of the current channel is suspended. when the mcu resumes normal operation, that channel is resampled and the conversion sequence is resumed. as the mcu exits wait mode, the a/d circuits are stable and valid results can be obtained on the first conversion. however, in stop mode, all analog bias currents are disabled and it is necessary to a llow a stabilization period when leaving stop mode. if stop mode is exited with a delay (dly = 1), there is enough time for these circuits to stabilize before the first conversion. if stop mode is exited with no delay (dly bit in option register = 0), allow 10 ms for the a/d circuitry to stabilize to avoid invalid results. 3.9 a/d control/status register all bits in this register can be read or written, except bit 7, which is a read-only status indicator, and bit 6, which always reads as 0. write to adctl to initiate a conversion. to quit a conversion in progress, write to this register and a new conver sion sequence begins immediately. ccf ? conversion complete flag a read-only status indicator, this bit is set when al l four a/d result registers contain valid conversion results. each time the adctl register is overwri tten, this bit is automatically cleared to 0 and a conversion sequence is started. in the continuous mode, ccf is set at the end of the first conversion sequence. bit 6 ? unimplemented always reads 0 scan ? continuous scan control bit address: $1030 bit 7654321bit 0 read: ccf scan mult cd cc cb ca write: reset: 0 0 indeterminate after reset = unimplemented figure 3-5. a/d control/status register (adctl)
a/d control/status register m68hc11e family data sheet, rev. 5.1 freescale semiconductor 63 when this control bit is clear, the four requested conversions are performed once to fill the four result registers. when this control bit is set, conversions are performed continuously with the result registers updated as data becomes available. mult ? multiple channel/single channel control bit when this bit is clear, the a/d converter system is configured to perform four consecutive conversions on the single channel specified by the four channel select bits cd:ca (bits [3:0] of the adctl register). when this bit is set, the a/d system is configur ed to perform a conversion on each of four channels where each result register corresponds to one channel. note when the multiple-channel continuous scan mode is used, extra care is needed in the design of circuitry drivi ng the a/d inputs. the charge on the capacitive dac array before the sample time is related to the voltage on the previously converted channel. a charge share situation exists between the internal dac capacitance and the ex ternal circuit capacitance. although the amount of charge involved is small, the rate at which it is repeated is every 64 s for an e clock of 2 mhz. the rc charging rate of the external circuit must be balanced against this charge sharing effect to avoid errors in accuracy. refer to m68hc11 reference manual, freescale document order number m68hc11rm/ad, for further information. cd:ca ? channel selects d:a bits refer to table 3-2 . when a multiple channel mode is selected (mult = 1), the two least significant channel select bits (cb and ca) have no meaning and the cd and cc bits specify which group of four channels is to be converted. table 3-2. a/d converter channel selection channel select control bits channel signal result in adrx if mult = 1 cd:cc:cb:ca 0000 an0 adr1 0001 an1 adr2 0010 an2 adr3 0011 an3 adr4 0100 an4 adr1 0101 an5 adr2 0110 an6 adr3 0111 an7 adr4 10xx reserved ? 1100 v rh (1) 1. used for factory testing adr1 1101 v rl (1) adr2 1110 (v rh )/2 (1) adr3 1111 reserved (1) adr4
analog-to-digital (a/d) converter m68hc11e family data sheet, rev. 5.1 64 freescale semiconductor 3.10 a/d converter result registers these read-only registers hold an 8-bit conversion resu lt. writes to these registers have no effect. data in the a/d converter result registers is valid when the ccf flag in the adctl register is set, indicating a conversion sequence is complete. if conver sion results are needed sooner, refer to figure 3-3 , which shows the a/d conversion sequence diagram. register name: analog-to-digital converter result register 1 address: $1031 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name: analog-to-digital converter result register 2 address: $1032 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name: analog-to-digital converter result register 3 address: $1033 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name: analog-to-digital converter result register 4 address: $1034 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset = unimplemented figure 3-6. analog-to-digital converter result registers (adr1?adr4)
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 65 chapter 4 central processor unit (cpu) 4.1 introduction features of the m68hc11 family include: central processor unit (cpu) architecture data types addressing modes instruction set special operations such as subroutine calls and interrupts the cpu is designed to treat all peripheral, input/o utput (i/o), and memory locations identically as addresses in the 64-kbyte memory map. this is referred to as memory-mapped i/o. there are no special instructions for i/o that are separate from those used for memory. this architecture also allows accessing an operand from an external memory lo cation with no execution time penalty. 4.2 cpu registers m68hc11 cpu registers are an integral part of the cpu and are not addressed as if they were memory locations. the seven register s, discussed in the followi ng paragraphs, are shown in figure 4-1 . figure 4-1. programming model 8-bit accumulators a & b 70 70 15 0 ab d ix iy sp pc 70 c v z n i h x s or 16-bit double accumulator d index register x index register y stack pointer program counter carry/borrow from msb overflow zero negative i-interrupt mask half carry (from bit 3) x-interrupt mask stop disable condition codes
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 66 freescale semiconductor 4.2.1 accumulators a, b, and d accumulators a and b are general-purpose 8-bit regist ers that hold operands and results of arithmetic calculations or data manipulations. for some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator d. although most instructions can use accumulators a or b interchangeably, these exceptions apply: the abx and aby instructions add the contents of 8-bit accumulator b to the contents of 16-bit register x or y, but there are no equivalent instructions that use a instead of b. the tap and tpa instructions transfer data from accumulator a to the condition code register or from the condition code register to accumulator a. however, there are no equivalent instructions that use b rather than a. the decimal adjust accumulator a (daa) instruct ion is used after binary-coded decimal (bcd) arithmetic operations, but there is no equival ent bcd instruction to adjust accumulator b. the add, subtract, and compare instructions associated with both a and b (aba, sba, and cba) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. 4.2.2 index register x (ix) the ix register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. the ix regi ster can also be used as a counter or as a temporary storage register. 4.2.3 index register y (iy) the 16-bit iy register performs an indexed mode function similar to that of the ix register. however, most instructions using the iy register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented. refer to 4.4 opcodes and operands for further information. 4.2.4 stack pointer (sp) the m68hc11 cpu has an automatic program stack. th is stack can be located anywhere in the address space and can be any size up to the amount of me mory available in the system. normally, the sp is initialized by one of the first instructions in an application program. the stack is configured as a data structure that grows downward from high memory to low memory. each time a new byte is pushed onto the stack, the sp is decremented. each time a byte is pulled from the stack, the sp is incremented. at any given time, the sp holds the 16-bit address of the next free location in the stack. figure 4-2 is a summary of sp operations. when a subroutine is called by a jump-to-subroutine (j sr) or branch-to- subroutine (bsr) instruction, the address of the instruction after the jsr or bsr is automatically pushed onto the stack, least significant byte first. when the subroutine is finished, a return -from-subroutine (rts) instruction is executed. the rts pulls the previously stacked return address from the stack and loads it into the program counter. execution then continues at this recovered return address. when an interrupt is recognized, the current instruct ion finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the cpu registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt.
cpu registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 67 at the end of the interrupt service routine, an return-from interrupt (rti) instruction is executed. the rti instruction causes the saved registers to be pull ed off the stack in reverse order. program execution resumes at the return address. certain instructions push and pull the a and b accumulators and the x and y index registers and are often used to preserve program context. for example, pus hing accumulator a onto the stack when entering a subroutine that uses accumulator a and then pulling ac cumulator a off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. figure 4-2. stacking operations sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $9d = jsr jsr, jump to subroutine dd next main instr. rtn direct pc main program $ad = jsr ff next main instr. rtn indexed, x pc main program $18 = pre ff next main instr. rtn indexed, y $ad = jsr pc main program $bd = pre ll next main instr. rtn indexed, y hh sp stack ccr sp+1 accb sp+2 acca sp+3 ix h sp+4 ix l sp+5 iy h sp+6 iy l sp+7 rtn h sp+8 sp+9 70 rtn l pc interrupt routine $3b = rti sp?9 stack ccr sp?8 accb sp?7 acca sp?6 ix h sp?5 ix l sp?4 iy h sp?3 iy l sp?2 rtn h sp?1 sp 70 rtn l pc main program $3f = swi pc main program $3e = wai swi, software interrupt wai, wait for interrupt rti, return from interrupt sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $8d = bsr pc main program $39 = rts bsr, branch to subroutine rts, return from subroutine sp stack rtn h sp+1 rtn l sp+2 70 legend: rtn = address of next instruction in main program to be executed upon return from subroutine rtn h = most significant byte of return address rtn l = least significant byte of return address = stack pointer position after operation is complete dd = 8-bit direct address ( $0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) is added to index hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr= signed relative offset $80 (?128) to $7f (+127) (offset relative to the address following the machine code offset byte)
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 68 freescale semiconductor 4.2.5 program counter (pc) the program counter, a 16-bit register, contains the address of the next instruction to be executed. after reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. see table 4-1 . 4.2.6 condition code register (ccr) this 8-bit register contains: five condition code indicators (c, v, z, n, and h), two interrupt masking bits (irq and xirq ) a stop disable bit (s) in the m68hc11 cpu, condition codes are updated automat ically by most instructions. for example, load accumulator a (ldaa) and store accumulator a (staa) instructions automatically set or clear the n, z, and v condition code flags. pushes, pulls, add b to x (abx), add b to y (aby), and transfer/exchange instructions do not affect the condition codes. refer to table 4-2 , which shows what condition codes are affected by a particular instruction. 4.2.6.1 carry/borrow (c) the c bit is set if the arithmetic logic unit (alu) perf orms a carry or borrow during an arithmetic operation. the c bit also acts as an error flag for multiply and divide operations. shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 4.2.6.2 overflow (v) the overflow bit is set if an operat ion causes an arithmetic overflow . otherwise, the v bit is cleared. 4.2.6.3 zero (z) the z bit is set if the result of an arithmetic, logi c, or data manipulation operation is 0. otherwise, the z bit is cleared. compare instructions do an internal implied subtraction and the condition codes, including z, reflect the results of that subtraction. a few operations (inx, dex, iny, and dey) affect the z bit and no other condition flags. fo r these operations, only = and conditions can be determined. 4.2.6.4 negative (n) the n bit is set if the result of an arithmetic, logi c, or data manipulation operation is negative (msb = 1). otherwise, the n bit is cleared. a result is said to be negative if its most significant bit (msb) is a 1. a quick way to test whether the contents of a memory location has the msb set is to load it into an accumulator and then check the status of the n bit. table 4-1. reset vector comparison mode por or reset pin clock monitor cop watchdog normal $fffe, f $fffc, d $fffa, b test or boot $bffe, f $bffc, d $bffa, b
data types m68hc11e family data sheet, rev. 5.1 freescale semiconductor 69 4.2.6.5 interrupt mask (i) the interrupt request (irq) mask (i bit) is a global mask that disables all ma skable interrupt sources. while the i bit is set, interrupts can become pending, but the operation of the cpu continues uninterrupted until the i bit is cleared. after any reset, the i bit is set by default and can only be cleared by a software instruction. when an interrupt is recognized, the i bit is set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, a return-from-interrupt instruction is normally executed, restoring the registers to the val ues that were present before the interrupt occurred. normally, the i bit is 0 after a return from interrupt is executed. although the i bit can be cleared within an interrupt service routine, "nesting" interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. refer to chapter 5 resets and interrupts . 4.2.6.6 half carry (h) the h bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an add, aba, or adc instruction. otherwise, the h bit is cl eared. half carry is used during bcd operations. 4.2.6.7 x interrupt mask (x) the xirq mask (x) bit disables interrupts from the xirq pin. after any reset, x is set by default and must be cleared by a software instruction. when an xirq interrupt is recognized, the x and i bits are set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, an rti instruction is normally executed, causing the registers to be restored to the values that were present before the interrupt occu rred. the x interrupt mask bit is set only by hardware (reset or xirq acknowledge). x is cleared only by program instructi on (tap, where the associated bit of a is 0; or rti, where bit 6 of the value loaded into the ccr from the stack has been cleared). there is no hardware action for clearing x. 4.2.6.8 stop disable (s) setting the stop disable (s) bit prevents the stop instruction from putting the m68hc11 into a low-power stop condition. if the stop instruction is encountered by the cpu while the s bit is set, it is treated as a no-operation (nop) instruction, and proces sing continues to the next instruction. s is set by reset; stop is disabled by default. 4.3 data types the m68hc11 cpu supports four data types: 1. bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes with the most significant by te at the lower value address. because the m68hc11 is an 8-bit cpu, there are no special requirements for alignment of instructions or operands.
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 70 freescale semiconductor 4.4 opcodes and operands the m68hc11 family of microcontrollers uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to provide each instruction with a range of addressing capabilities. on ly 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. a 4-page opcode map has been implemented to expand the number of instructions. an additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. as its name implies, the additional byte precedes the opcode. a complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. the operands contain information the cpu needs for executing the instruction. complete instructions can be from one to five bytes long. 4.5 addressing modes six addressing modes can be used to access memory: immediate direct extended indexed inherent relative these modes are detailed in the following paragraphs . all modes except inherent mode use an effective address. the effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed. t he effective address can be specified within an instruction, or it can be calculated. 4.5.1 immediate in the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. the number of bytes following the opcode matches the size of the register or memory location being operated on. there are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. the effective address is the address of the byte following the instruction. 4.5.2 direct in the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. addresses $00?$ff are thus accessed directly, using 2-byte instructio ns. execution time is reduced by eliminating the additional memory access required for the high-or der address byte. in most applications, this 256-byte area is reserved for frequently referenced data. in m68hc11 mcus, the memory map can be configured for combinations of internal registers, ra m, or external memory to occupy these addresses.
instruction set m68hc11e family data sheet, rev. 5.1 freescale semiconductor 71 4.5.3 extended in the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. these are 3-byte instructions (or 4-byte instructions if a prebyte is required). one or two bytes are needed for the opcode and two for the effective address. 4.5.4 indexed in the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (ix or iy). the sum is the effective address. this addressing mode allows referencing any memory location in the 64-kbyte addr ess space. these are 2- to 5-byte instructions, depending on whether or not a prebyte is required. 4.5.5 inherent in the inherent addressing mode, all the information neces sary to execute the instruction is contained in the opcode. operations that use only the index register s or accumulators, as well as control instructions with no arguments, are included in this addressing mode. these are 1- or 2-byte instructions. 4.5.6 relative the relative addressing mode is used only for branch in structions. if the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. otherwise, control proceeds to the next instruction. these are usually 2-byte instructions. 4.6 instruction set refer to table 4-2 , which shows all the m68hc11 instructions in all possible addressing modes. for each instruction, the table shows the operand constructi on, the number of machine code bytes, and execution time in cpu e-clock cycles.
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 72 freescale semiconductor table 4-2. instruction set (sheet 1 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c aba add accumulators a + b ? ainh1b?2?? ? ? ???? abx add b to x ix + (00 : b) ? ix inh 3a ? 3 ???????? aby add b to y iy + (00 : b) ? iy inh 18 3a ? 4 ???????? adca (opr) add with carry to a a + m + c ? aa imm adir aext aind,x aind,y 89 99 b9 a9 18 a9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adcb (opr) add with carry to b b + m + c ? bb imm bdir bext bind,x bind,y c9 d9 f9 e9 18 e9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adda (opr) add memory to a a + m ? a a imm adir aext aind,x aind,y 8b 9b bb ab 18 ab ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addb (opr) add memory to b b + m ? bbimm bdir bext bind,x bind,y cb db fb eb 18 eb ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addd (opr) add 16-bit to d d + (m : m + 1) ? dimm dir ext ind,x ind,y c3 d3 f3 e3 18 e3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? anda (opr) and a with memory a m ? aa imm a dir a ext aind,x aind,y 84 94 b4 a4 18 a4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? andb (opr) and b with memory b m ? bbimm bdir bext bind,x bind,y c4 d4 f4 e4 18 e4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? asl (opr) arithmetic shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? asla arithmetic shift left a a inh 48 ? 2 ???? ???? aslb arithmetic shift left b b inh 58 ? 2 ???? ???? asld arithmetic shift left d inh 05 ? 3 ? ? ? ? ???? asr arithmetic shift right ext ind,x ind,y 77 67 18 67 hh ll ff ff 6 6 7 ???? ???? asra arithmetic shift right a a inh 47 ? 2 ???? ???? asrb arithmetic shift right b b inh 57 ? 2 ???? ???? bcc (rel) branch if carry clear ? c = 0 rel 24 rr 3 ???????? bclr (opr) (msk) clear bit(s) m (mm ) ? m dir ind,x ind,y 15 1d 18 1d dd mm ff mm ff mm 6 7 8 ???? ?? 0? bcs (rel) branch if carry set ? c = 1 rel 25 rr 3 ???????? beq (rel) branch if = zero ? z = 1 rel 27 rr 3 ? ? ? ? ? ? ? ? bge (rel) branch if ? zero ? n v = 0 rel 2c rr 3 ???????? c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0
instruction set m68hc11e family data sheet, rev. 5.1 freescale semiconductor 73 bgt (rel) branch if > zero ? z + (n v) = 0 rel 2e rr 3 ???????? bhi (rel) branch if higher ? c + z = 0 rel 22 rr 3 ???????? bhs (rel) branch if higher or same ? c = 0 rel 24 rr 3 ???????? bita (opr) bit(s) test a with memory a m a imm adir aext aind,x aind,y 85 95 b5 a5 18 a5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? bitb (opr) bit(s) test b with memory b m b imm bdir bext bind,x bind,y c5 d5 f5 e5 18 e5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ble (rel) branch if ? zero ? z + (n v) = 1 rel 2f rr 3 ???????? blo (rel) branch if lower ? c = 1 rel 25 rr 3 ???????? bls (rel) branch if lower or same ? c + z = 1 rel 23 rr 3 ???????? blt (rel) branch if < zero ? n v = 1 rel 2d rr 3 ???????? bmi (rel) branch if minus ? n = 1 rel 2b rr 3 ???????? bne (rel) branch if not = zero ? z = 0 rel 26 rr 3 ???????? bpl (rel) branch if plus ? n = 0 rel 2a rr 3 ???????? bra (rel) branch always ? 1 = 1 rel 20 rr 3 ???????? brclr(opr) (msk) (rel) branch if bit(s) clear ? m mm = 0 dir ind,x ind,y 13 1f 18 1f dd mm rr ff mm rr ff mm rr 6 7 8 ???????? brn (rel) branch never ? 1 = 0 rel 21 rr 3 ???????? brset(opr) (msk) (rel) branch if bit(s) set ? (m ) mm = 0 dir ind,x ind,y 12 1e 18 1e dd mm rr ff mm rr ff mm rr 6 7 8 ???????? bset (opr) (msk) set bit(s) m + mm ? mdir ind,x ind,y 14 1c 18 1c dd mm ff mm ff mm 6 7 8 ???? ?? 0? bsr (rel) branch to subroutine see figure 3?2 rel 8d rr 6 ???????? bvc (rel) branch if overflow clear ? v = 0 rel 28 rr 3 ???????? bvs (rel) branch if overflow set ? v = 1 rel 29 rr 3 ???????? cba compare a to b a ? b inh 11 ? 2 ? ? ? ? ???? clc clear carry bit 0 ? c inh 0c ? 2 ??????? 0 cli clear interrupt mask 0 ? i inh 0e ? 2 ??? 0 ???? clr (opr) clear memory byte 0 ? mext ind,x ind,y 7f 6f 18 6f hh ll ff ff 6 6 7 ???? 0 1 0 0 clra clear accumulator a 0 ? a a inh 4f ? 2 ? ? ? ? 0 1 0 0 clrb clear accumulator b 0 ? b b inh 5f ? 2 ? ? ? ? 0 1 0 0 clv clear overflow flag 0 ? v inh 0a ? 2 ?????? 0 ? cmpa (opr) compare a to memory a ? m a imm adir aext aind,x aind,y 81 91 b1 a1 18 a1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? table 4-2. instruction set (sheet 2 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 74 freescale semiconductor cmpb (opr) compare b to memory b ? m b imm bdir bext bind,x bind,y c1 d1 f1 e1 18 e1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? com (opr) ones complement memory byte $ff ? m ? mext ind,x ind,y 73 63 18 63 hh ll ff ff 6 6 7 ???? ?? 01 coma ones complement a $ff ? a ? aa inh 43 ? 2 ???? ?? 01 comb ones complement b $ff ? b ? bb inh 53 ? 2 ???? ?? 01 cpd (opr) compare d to memory 16-bit d ? m : m + 1 imm dir ext ind,x ind,y 1a 83 1a 93 1a b3 1a a3 cd a3 jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? cpx (opr) compare x to memory 16-bit ix ? m : m + 1 imm dir ext ind,x ind,y 8c 9c bc ac cd ac jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? cpy (opr) compare y to memory 16-bit iy ? m : m + 1 imm dir ext ind,x ind,y 18 8c 18 9c 18 bc 1a ac 18 ac jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? daa decimal adjust a adjust sum to bcd inh 19 ? 2 ? ? ? ? ???? dec (opr) decrement memory byte m ? 1 ? mext ind,x ind,y 7a 6a 18 6a hh ll ff ff 6 6 7 ???? ??? ? deca decrement accumulator a a ? 1 ? aainh 4a ? 2???? ??? ? decb decrement accumulator b b ? 1 ? bbinh 5a ? 2???? ??? ? des decrement stack pointer sp ? 1 ? sp inh 34 ? 3 ???????? dex decrement index register x ix ? 1 ? ix inh 09 ? 3 ? ? ? ? ? ? ?? dey decrement index register y iy ? 1 ? iy inh 18 09 ? 4 ? ? ? ? ? ? ?? eora (opr) exclusive or a with memory a m ? a a imm adir aext aind,x aind,y 88 98 b8 a8 18 a8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? eorb (opr) exclusive or b with memory b m ? b b imm bdir bext bind,x bind,y c8 d8 f8 e8 18 e8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? fdiv fractional divide 16 by 16 d / ix ? ix; r ? d inh 03 ? 41 ????? ??? idiv integer divide 16 by 16 d / ix ? ix; r ? d inh 02 ? 41 ????? ? 0 ? inc (opr) increment memory byte m + 1 ? mext ind,x ind,y 7c 6c 18 6c hh ll ff ff 6 6 7 ???? ??? ? inca increment accumulator a a + 1 ? a a inh 4c ? 2 ? ? ? ? ??? ? table 4-2. instruction set (sheet 3 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c
instruction set m68hc11e family data sheet, rev. 5.1 freescale semiconductor 75 incb increment accumulator b b + 1 ? b b inh 5c ? 2 ? ? ? ? ??? ? ins increment stack pointer sp + 1 ? sp inh 31 ? 3 ???????? inx increment index register x ix + 1 ? ix inh 08 ? 3 ????? ? ?? iny increment index register y iy + 1 ? iy inh 18 08 ? 4 ????? ? ?? jmp (opr) jump see figure 3?2 ext ind,x ind,y 7e 6e 18 6e hh ll ff ff 3 3 4 ???????? jsr (opr) jump to subroutine see figure 3?2 dir ext ind,x ind,y 9d bd ad 18 ad dd hh ll ff ff 5 6 6 7 ???????? ldaa (opr) load accumulator a m ? a a imm a dir a ext a ind,x a ind,y 86 96 b6 a6 18 a6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ldab (opr) load accumulator b m ? b b imm b dir b ext b ind,x b ind,y c6 d6 f6 e6 18 e6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ldd (opr) load double accumulator d m ? a,m + 1 ? bimm dir ext ind,x ind,y cc dc fc ec 18 ec jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? lds (opr) load stack pointer m : m + 1 ? sp imm dir ext ind,x ind,y 8e 9e be ae 18 ae jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldx (opr) load index register x m : m + 1 ? ix imm dir ext ind,x ind,y ce de fe ee cd ee jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldy (opr) load index register y m : m + 1 ? iy imm dir ext ind,x ind,y 18 ce 18 de 18 fe 1a ee 18 ee jj kk dd hh ll ff ff 4 5 6 6 6 ???? ?? 0? lsl (opr) logical shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? lsla logical shift left a a inh 48 ? 2 ???? ???? lslb logical shift left b b inh 58 ? 2 ???? ???? lsld logical shift left double inh 05 ? 3 ? ? ? ? ???? lsr (opr) logical shift right ext ind,x ind,y 74 64 18 64 hh ll ff ff 6 6 7 ???? 0 ??? lsra logical shift right a a inh 44 ? 2 ???? 0 ??? lsrb logical shift right b b inh 54 ? 2 ???? 0 ??? table 4-2. instruction set (sheet 4 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 76 freescale semiconductor lsrd logical shift right double inh 04 ? 3 ? ? ? ? 0 ??? mul multiply 8 by 8 a ? b ? d inh 3d ? 10 ??????? ? neg (opr) two?s complement memory byte 0 ? m ? mext ind,x ind,y 70 60 18 60 hh ll ff ff 6 6 7 ???? ???? nega two?s complement a 0 ? a ? aainh 40 ? 2???? ???? negb two?s complement b 0 ? b ? bbinh 50 ? 2???? ???? nop no operation no operation inh 01 ? 2 ? ? ? ? ? ? ? ? oraa (opr) or accumulator a (inclusive) a + m ? a a imm adir aext aind,x aind,y 8a 9a ba aa 18 aa ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? orab (opr) or accumulator b (inclusive) b + m ? b b imm bdir bext bind,x bind,y ca da fa ea 18 ea ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? psha push a onto stack a ? stk,sp = sp ? 1 a inh 36 ? 3 ? ? ? ? ? ? ? ? pshb push b onto stack b ? stk,sp = sp ? 1 b inh 37 ? 3 ? ? ? ? ? ? ? ? pshx push x onto stack (lo first) ix ? stk,sp = sp ? 2 inh 3c ? 4 ???????? pshy push y onto stack (lo first) iy ? stk,sp = sp ? 2 inh 18 3c ? 5 ???????? pula pull a from stack sp = sp + 1, a ? stka inh 32 ? 4 ???????? pulb pull b from stack sp = sp + 1, b ? stkb inh 33 ? 4 ???????? pulx pull x from stack (hi first) sp = sp + 2, ix ? stk inh 38 ? 5 ???????? puly pull y from stack (hi first) sp = sp + 2, iy ? stk inh 18 38 ? 6 ???????? rol (opr) rotate left ext ind,x ind,y 79 69 18 69 hh ll ff ff 6 6 7 ???? ???? rola rotate left a a inh 49 ? 2 ? ? ? ? ???? rolb rotate left b b inh 59 ? 2 ? ? ? ? ???? ror (opr) rotate right ext ind,x ind,y 76 66 18 66 hh ll ff ff 6 6 7 ???? ???? rora rotate right a a inh 46 ? 2 ? ? ? ? ???? rorb rotate right b b inh 56 ? 2 ? ? ? ? ???? rti return from interrupt see figure 3?2 inh 3b ? 12 ??????? rts return from subroutine see figure 3?2 inh 39 ? 5 ? ? ? ? ? ? ? ? sba subtract b from a a ? b ? a inh 10 ? 2 ???? ???? table 4-2. instruction set (sheet 5 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0
instruction set m68hc11e family data sheet, rev. 5.1 freescale semiconductor 77 sbca (opr) subtract with carry from a a ? m ? c ? aa imm adir aext aind,x aind,y 82 92 b2 a2 18 a2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sbcb (opr) subtract with carry from b b ? m ? c ? bb imm bdir bext bind,x bind,y c2 d2 f2 e2 18 e2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sec set carry 1 ? c inh 0d ? 2 ??????? 1 sei set interrupt mask 1 ? i inh 0f ? 2 ??? 1 ???? sev set overflow flag 1 ? v inh 0b ? 2 ?????? 1 ? staa (opr) store accumulator a a ? madir aext aind,x aind,y 97 b7 a7 18 a7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? stab (opr) store accumulator b b ? mbdir bext bind,x bind,y d7 f7 e7 18 e7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? std (opr) store accumulator d a ? m, b ? m + 1 dir ext ind,x ind,y dd fd ed 18 ed dd hh ll ff ff 4 5 5 6 ???? ?? 0? stop stop internal clocks ? inh cf ? 2 ???????? sts (opr) store stack pointer sp ? m : m + 1 dir ext ind,x ind,y 9f bf af 18 af dd hh ll ff ff 4 5 5 6 ???? ?? 0? stx (opr) store index register x ix ? m : m + 1 dir ext ind,x ind,y df ff ef cd ef dd hh ll ff ff 4 5 5 6 ???? ?? 0? sty (opr) store index register y iy ? m : m + 1 dir ext ind,x ind,y 18 df 18 ff 1a ef 18 ef dd hh ll ff ff 5 6 6 6 ???? ?? 0? suba (opr) subtract memory from a a ? m ? aaimm adir aext aind,x aind,y 80 90 b0 a0 18 a0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subb (opr) subtract memory from b b ? m ? baimm adir aext aind,x aind,y c0 d0 f0 e0 18 e0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subd (opr) subtract memory from d d ? m : m + 1 ? dimm dir ext ind,x ind,y 83 93 b3 a3 18 a3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? swi software interrupt see figure 3?2 inh 3f ? 14 ? ? ? 1 ? ? ? ? tab transfer a to b a ? b inh 16 ? 2 ???? ?? 0? tap transfer a to cc register a ? ccr inh 06 ? 2 ??????? tba transfer b to a b ? a inh 17 ? 2 ???? ?? 0? test test (only in test modes) address bus counts inh 00 ? * ? ? ? ? ? ? ? ? tpa transfer cc register to a ccr ? a inh 07 ? 2 ???????? tst (opr) test for zero or minus m ? 0 ext ind,x ind,y 7d 6d 18 6d hh ll ff ff 6 6 7 ???? ?? 00 table 4-2. instruction set (sheet 6 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c
central processor unit (cpu) m68hc11e family data sheet, rev. 5.1 78 freescale semiconductor tsta test a for zero or minus a ? 0 a inh 4d ? 2 ? ? ? ? ?? 00 tstb test b for zero or minus b ? 0 b inh 5d ? 2 ? ? ? ? ?? 00 tsx transfer stack pointer to x sp + 1 ? ix inh 30 ? 3 ???????? tsy transfer stack pointer to y sp + 1 ? iy inh 18 30 ? 4 ???????? txs transfer x to stack pointer ix ? 1 ? sp inh 35 ? 3 ???????? tys transfer y to stack pointer iy ? 1 ? sp inh 18 35 ? 4 ???????? wai wait for interrupt stack regs & wait inh 3e ? ** ? ? ? ? ? ? ? ? xgdx exchange d with x ix ? d, d ? ix inh 8f ? 3 ???????? xgdy exchange d with y iy ? d, d ? iy inh 18 8f ? 4 ???????? cycle * infinity or until reset occurs ** 12 cycles are used beginning with the opcode fetch. a wait stat e is entered which remains in effect for an integer number of mpu e-clock cycles (n) until an interrupt is recognized. finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). operands dd = 8-bit direct address ($0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) (is added to index) hh = high-order byte of 16-bit extended address ii = one byte of immediate data jj = high-order byte of 16-bit immediate data kk = low-order byte of 16-bit immediate data ll = low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = signed relative offset $80 (?128) to $7f (+127) (offset relative to address following machine code offset byte)) operators ( ) contents of register shown inside parentheses ? is transferred to ? is pulled from stack ? is pushed onto stack boolean and + arithmetic addition symbol except where used as inclusive-or symbol in boolean formula exclusive-or ? multiply : concatenation ? arithmetic subtraction symbol or negation symbol (two?s complement) condition codes ? bit not changed 0 bit always cleared 1 bit always set ? bit cleared or set, depending on operation bit can be cleared, cannot become set table 4-2. instruction set (sheet 7 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 79 chapter 5 resets and interrupts 5.1 introduction resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. a reset immediately stops execution of the current instruction and forces the program counter to a known starting address. internal registers and control bits are initialized so the mcu can resume executing instructions. an interrupt temporarily suspends normal program execution while an interrupt service routine is being executed. after an interrupt has been serviced, the main program resumes as if there had been no interruption. 5.2 resets the four possible sources of reset are: power-on reset (por) external reset (reset ) computer operating properly (cop) reset clock monitor reset por and reset share the normal reset vector. cop reset and the clock monitor reset each has its own vector. 5.2.1 power-on reset (por) a positive transition on v dd generates a power-on reset (por), which is used only for power-up conditions. por cannot be used to detect drops in power supply voltages. a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if reset is at logical 0 at the end of 4064 t cyc , the cpu remains in the reset condition until reset goes to logical 1. the por circuit only initializes internal circuitry during cold starts. refer to figure 1-7. external reset circuit . note it is important to protect the mcu during power transitions. most m68hc11 systems need an external ci rcuit that holds the reset pin low whenever v dd is below the minimum operating le vel. this external voltage level detector, or other external reset circuits, are the usual source of reset in a system.
resets and interrupts m68hc11e family data sheet, rev. 5.1 80 freescale semiconductor 5.2.2 external reset (reset ) the cpu distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two e-clock cycles a fter an internal device releases reset. when a reset condition is sensed, the reset pin is driven low by an internal device for four e-clock cycles, then released. two e-clock cycles later it is sampled. if the pin is still he ld low, the cpu assumes that an external reset has occurred. if the pin is high, it indica tes that the reset was initiated internally by either the cop system or the clock monitor. caution do not connect an external resistor capacitor (rc) power-up delay circuit to the reset pin of m68hc11 devices because the circuit charge ti me constant can cause the device to misinterpret the type of reset that occurred. 5.2.3 computer operat ing properly (cop) reset the mcu includes a cop system to help protect agai nst software failures. when the cop is enabled, the software is responsible for keeping a free-running wa tchdog timer from timing out. when the software is no longer being executed in the intended sequence, a system reset is initiated. the state of the nocop bit in the config register determines whether the cop system is enabled or disabled. to change the enable status of the cop syst em, change the contents of the config register and then perform a system reset. in the special test and bootstrap operating modes, the cop system is initially inhibited by the disable resets (disr) c ontrol bit in the test1 register. the disr bit can subsequently be written to 0 to enable cop resets. the cop timer rate control bits cr [1:0] in the option register determine the cop timeout period. the system e clock is divided by 2 15 and then further scaled by a factor shown in table 5-1 . after reset, these bits are 0, which selects the fastest timeout period. in normal operating modes, these bits can be written only once within 64 bus cycles after reset. table 5-1. cop timer rate select cr[1:0] divide e/2 15 by xtal = 4.0 mhz timeout ? 0 ms, + 32.8 ms xtal = 8.0 mhz timeout ? 0 ms, + 16.4 ms xtal = 12.0 mhz timeout ? 0 ms, + 10.9 ms xtal = 16.0 mhz timeout ? 0 ms, + 8.2 ms 0 0 1 32.768 ms 16.384 ms 10.923 ms 8.19 ms 0 1 4 131.072 ms 65.536 ms 43.691 ms 32.8 ms 1 0 16 524.28 ms 262.14 ms 174.76 ms 131 ms 1 1 64 2.098 s 1.049 s 699.05 ms 524 ms e = 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz
resets m68hc11e family data sheet, rev. 5.1 freescale semiconductor 81 complete this 2-step reset sequence to service the cop timer: 1. write $55 to coprst to arm the cop timer clearing mechanism. 2. write $aa to coprst to clear the cop timer. performing instructions between t hese two steps is possible as long as both steps are completed in the correct sequence before the timer times out. 5.2.4 clock monitor reset the clock monitor circuit is based on an internal resi stor capacitor (rc) time delay. if no mcu clock edges are detected within this rc time delay, the clo ck monitor can optionally generate a system reset. the clock monitor function is enabled or disabled by the cm e control bit in the option register. the presence of a timeout is determined by the rc delay, which al lows the clock monitor to operate without any mcu clocks. clock monitor is used as a backup for the cop system. because the cop needs a clock to function, it is disabled when the clock stops. therefore, the clock m onitor system can detect cloc k failures not detected by the cop system. semiconductor wafer processing causes variations of the rc timeout values between individual devices. an e-clock frequency below 10 khz is detected as a cl ock monitor error. an e-clock frequency of 200 khz or more prevents clock monitor errors. using the clock monitor function when the e-clock is below 200 khz is not recommended. special considerations are needed when a stop instru ction is executed and the clock monitor is enabled. because the stop function causes the clocks to be halted, the clock monitor function generates a reset sequence if it is enabled at the time the stop mode was initiated. before executing a stop instruction, clear the cme bit in the option register to 0 to disa ble the clock monitor. after recovery from stop, set the cme bit to logic 1 to enable the clock monitor. al ternatively, executing a stop instruction with the cme bit set to logic 1 can be used as a software initiated reset. address $103a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0000000 figure 5-1. arm/reset cop timer circuitry register (coprst)
resets and interrupts m68hc11e family data sheet, rev. 5.1 82 freescale semiconductor 5.2.5 system configur ation options register adpu ? analog-to-digital converter power-up bit refer to chapter 3 analog-to-digital (a/d) converter . csel ? clock select bit refer to chapter 3 analog-to-digital (a/d) converter . irqe ? configure irq for edge-sensitive-only operation bit 0 = irq is configured for level-sensitive operation. 1 = irq is configured for edge-s ensitive-only operation. dly ? enable oscillator startup delay bit refer to chapter 2 operating modes and on-chip memory and chapter 3 analog-to-digital (a/d) converter . cme ? clock monitor enable bit this control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system cloc k is slow or absent. when it is clear, the clock monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. reset clears the cme bit. 0 = clock monitor circuit disabled 1 = slow or stopped clocks cause reset bit 2 ? unimplemented always reads 0 cr[1:0] ? cop timer rate select bit the internal e clock is first divided by 2 15 before it enters the cop watchdog system. these control bits determine a scaling factor for the watchdog timer. see table 5-1 for specific timeout settings. address: $1039 bit 7654321bit 0 read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset: 0 0010000 1. can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes = unimplemented figure 5-2. system configuration options register (option)
effects of reset m68hc11e family data sheet, rev. 5.1 freescale semiconductor 83 5.2.6 configurati on control register ee[3:0] ? eeprom mapping bits ee[3:0] apply only to mc68hc811e2. refer to chapter 2 operating modes and on-chip memory . nosec ? security mode disable bit refer to chapter 2 operating modes and on-chip memory . nocop ? cop system disable bit 0 = cop enabled (forces reset on timeout) 1 = cop disabled (does not force reset on timeout) romon ? rom (eprom) enable bit refer to chapter 2 operating modes and on-chip memory . eeon ? eeprom enable bit refer to chapter 2 operating modes and on-chip memory . 5.3 effects of reset when a reset condition is recognized, the internal registers and control bits are forced to an initial state. depending on the cause of the reset and the operating mode, the reset vector can be fetched from any of six possible locations. refer to table 5-2 . these initial states then control on-chip peripheral systems to force them to known startup states, as described in the foll owing subsections. 5.3.1 central pr ocessor unit (cpu) after reset, the central processor unit (cpu) fetches the restart vector from the appropriate address during the first three cycles and begins executing instruct ions. the stack pointer and other cpu registers are indeterminate immediately after reset; however, the x and i interrupt mask bits in the condition code register (ccr) are set to mask any interrupt requests. also, the s bit in the ccr is set to inhibit stop mode. address: $103f bit 7654321bit 0 read: ee3 ee2 ee1 ee0 nosec nocop romon eeon write: reset: 0 0001111 figure 5-3. configuration control register (config) table 5-2. reset cause, reset vector, and operating mode cause of reset normal mode vector special test or bootstrap por or reset pin $fffe, ffff $bffe, $bfff clock monitor failure $fffc, fffd $bffc, $bffd cop watchdog timeout $fffa, fffb $bffa, $bffb
resets and interrupts m68hc11e family data sheet, rev. 5.1 84 freescale semiconductor 5.3.2 memory map after reset, the init register is initialized to $01, mapping the ram at $00 and the control registers at $1000. for the mc68hc811e2, the config re gister resets to $ff. eeprom m apping bits (ee[3:0]) place the eeprom at $f800. refer to the memory map diagra m for mc68hc811e2 in chapter 2 operating modes and on-chip memory . 5.3.3 timer during reset, the timer system is initialized to a co unt of $0000. the prescaler bits are cleared, and all output compare registers are initialized to $ffff. all input capture registers are indeterminate after reset. the output compare 1 mask (oc1m) register is cleared so that successful oc1 compares do not affect any i/o pins. the other four output compares are configured so that they do not affect any i/o pins on successful compares. all input capture edge-detec tor circuits are configured for capture disabled operation. the timer overflow interrupt flag and all eigh t timer function interrupt flags are cleared. all nine timer interrupts are disabled because their mask bits have been cleared. the i4/o5 bit in the pactl register is cleared to configure the i4/o5 function as oc5; however, the om5:ol5 control bits in the tctl1 register ar e clear so oc5 does not control the pa3 pin. 5.3.4 real-time interrupt (rti) the real-time interrupt flag (rtif) is cleared and automatic hardware interrupts are masked. the rate control bits are cleared after reset and can be initialized by software before the real-time interrupt (rti) system is used. 5.3.5 pulse accumulator the pulse accumulator system is disabled at reset so that the pulse accumulator input (pai) pin defaults to being a general-purpose input pin. 5.3.6 computer operating properly (cop) the cop watchdog system is enabled if the nocop cont rol bit in the config register is cleared and disabled if nocop is set. the cop rate is set for the shortest duration timeout. 5.3.7 serial communic ations interface (sci) the reset condition of the sci system is independent of the operating mode. at reset, the sci baud rate control register (baud) is initialized to $04. al l transmit and receive interrupts are masked and both the transmitter and receiver are disabled so the port pins default to being general-purpose i/o lines. the sci frame format is initialized to an 8-bit character size. the send break and receiver wakeup functions are disabled. the tdre and tc status bits in the sci stat us register (scsr) are bot h 1s, indicating that there is no transmit data in either the transmit data register or the transmit serial shift register. the rdrf, idle, or, nf, fe, pf, and raf receive-related status bits in the sci control register 2 (sccr2) are cleared. 5.3.8 serial perip heral interface (spi) the spi system is disabled by reset. the port pi ns associated with this function default to being general-purpose i/o lines.
reset and interrupt priority m68hc11e family data sheet, rev. 5.1 freescale semiconductor 85 5.3.9 analog-to-dig ital (a/d) converter the analog-to-digital (a/d) converter configuration is indeterminate after reset. the adpu bit is cleared by reset, which disables the a/d system. the conversion complete flag is indeterminate. 5.3.10 system the eeprom programming cont rols are disabled, so the memory sy stem is configured for normal read operation. psel[3:0] are init ialized with the value %0110, causing the external irq pin to have the highest i-bit interrupt priority. the irq pin is configured for level-sensitive operation (for wired-or systems). the rboot, smod, and mda bits in the hp rio register reflect the status of the modb and moda inputs at the rising edge of reset. moda and modb inputs select one of the four operating modes. after reset, writing smod and mda in special modes causes the mcu to change operating modes. refer to the description of hprio register in chapter 2 operating modes and on-chip memory for a detailed description of smod and mda. the dly control bit is set to specify that an oscillator startup delay is imposed upon recovery from stop mode. the clock moni tor system is disabled because cme is cleared. 5.4 reset and interrupt priority resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. any maskable inte rrupt can be given priority over other maskable interrupts. the first six interrupt sources are not maskable. the priority arrangement for these sources is: 1. por or reset pin 2. clock monitor reset 3. cop watchdog reset 4. xirq interrupt 5. illegal opcode interrupt 6. software interrupt (swi) the maskable interrupt sources have this priority arrangement: 1. irq 2. real-time interrupt 3. timer input capture 1 4. timer input capture 2 5. timer input capture 3 6. timer output compare 1 7. timer output compare 2 8. timer output compare 3 9. timer output compare 4 10. timer input capture 4/output compare 5 11. timer overflow 12. pulse accumulator overflow 13. pulse accumulator input edge 14. spi transfer complete 15. sci system (refer to figure 5-7 )
resets and interrupts m68hc11e family data sheet, rev. 5.1 86 freescale semiconductor any one of these interrupts can be assigned the highes t maskable interrupt priority by writing the appropriate value to the psel bits in the hprio regi ster. otherwise, the priority arrangement remains the same. an interrupt that is assigned hi ghest priority is still subject to gl obal masking by the i bit in the ccr, or by any associated local bits. interrupt vectors are not affected by priority assignment. to avoid race conditions, hprio can be wri tten only while i-bit interrupts are inhibited. 5.4.1 highest priority in terrupt and miscellaneous register rboot ? read bootstrap rom bit has meaning only when the smod bit is a 1 (bootstr ap mode or special test mode). at all other times this bit is clear and cannot be written. refer to chapter 2 operating modes and on-chip memory for more information. smod ? special mode select bit this bit reflects the inverse of the modb input pin at the rising edge of reset. refer to chapter 2 operating modes and on-chip memory for more information. mda ? mode select a bit the mode select a bit reflects the status of the moda input pin at the rising edge of reset. refer to chapter 2 operating m odes and on-chip memory for more information. irvne ? internal read visibility/not e bit the irvne control bit allows internal read accesses to be available on the external data bus during operation in expanded modes. in single-chip an d bootstrap modes, irvne determines whether the e clock is driven out an external pin. for the mc68hc811e2, this bit is irv and only controls internal read visibility. refer to chapter 2 operating m odes and on-chip memory for more information. psel[3:0] ? priority select bits these bits select one interrupt source to be el evated above all other i-bit-related sources and can be written only while the i bit in the ccr is set (interrupts disabled). address: $103c bit 7654321bit 0 read: rboot (1) smod (1) mda (1) irvne psel2 psel2 psel1 psel0 write: reset: single chip:00000110 expanded:00100110 bootstrap:11000110 special test:01110110 1. the values of the rboot, smod, and mda re set bits depend on the mode selected at the reset pin rising edge. refer to table 2-1. hardware mode select summary . figure 5-4. highest priority i-bit interrupt and miscellaneous register (hprio)
interrupts m68hc11e family data sheet, rev. 5.1 freescale semiconductor 87 5.5 interrupts the mcu has 18 interrupt vectors that support 22 interrupt sources. the 15 maskable interrupts are generated by on-chip peripheral systems. these interrupts are recognized when the global interrupt mask bit (i) in the condition code regi ster (ccr) is clear. the three non-ma skable interrupt sources are illegal opcode trap, software interrupt, and xirq pin. refer to table 5-4 , which shows the interrupt sources and vector assignments for each source. for some interrupt sources, such as the sci interr upts, the flags are automatically cleared during the normal course of responding to the interrupt requests . for example, the rdrf flag in the sci system is cleared by the automatic clearing me chanism consisting of a read of t he sci status register while rdrf is set, followed by a read of the sci data register. the normal response to an rdrf interrupt request would be to read the sci status register to check fo r receive errors, then to read the received data from the sci data register. these steps satisfy the auto matic clearing mechanism without requiring special instructions. table 5-3. highest priority interrupt selection psel[3:0] interrupt source promoted 0 0 0 0 timer overflow 0 0 0 1 pulse accumulator overflow 0 0 1 0 pulse accumulator input edge 0 0 1 1 spi serial transfer complete 0 1 0 0 sci serial system 0 1 0 1 reserved (default to irq ) 0 1 1 0 irq (external pin or parallel i/o) 0 1 1 1 real-time interrupt 1 0 0 0 timer input capture 1 1 0 0 1 timer input capture 2 1 0 1 0 timer input capture 3 1 0 1 1 timer output compare 1 1 1 0 0 timer output compare 2 1 1 0 1 timer output compare 3 1 1 1 0 timer output compare 4 1 1 1 1 timer input capture 4/output compare 5
resets and interrupts m68hc11e family data sheet, rev. 5.1 88 freescale semiconductor 5.5.1 interrupt recogni tion and register stacking an interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global mask bit in the ccr. once an interrupt source is re cognized, the cpu responds at the completion of the instruction being executed. interrupt latency varies according to the number of cycles required to complete the current instruction. when the cpu begins to service an interrupt, the contents of the cpu registers are pushed onto the stack in the order shown in table 5-5 . after the ccr value is stacked, the i bit and the x bit, if xirq is pending, are set to inhibit further interrupts. the interrupt vector for the highest priority pending source is fetched and execution conti nues at the address specified by the vector. at the table 5-4. interrupt and reset vector assignments vector address interrupt source ccr mask bit local mask ffc0, c1 ? ffd4, d5 reserved ? ? ffd6, d7 sci serial system sci receive data register full sci receiver overrun sci transmit data register empty sci transmit complete sci idle line detect i rie rie tie tcie ilie ffd8, d9 spi serial transfer complete i spie ffda, db pulse accumulator input edge i paii ffdc, dd pulse accumulator overflow i paovi ffde, df timer overflow i toi ffe0, e1 timer input capture 4/output compare 5 i i4/o5i ffe2, e3 timer output compare 4 i oc4i ffe4, e5 timer output compare 3 i oc3i ffe6, e7 timer output compare 2 i oc2i ffe8, e9 timer output compare 1 i oc1i ffea, eb timer input capture 3 i ic3i ffec, ed timer input capture 2 i ic2i ffee, ef timer input capture 1 i ic1i fff0, f1 real-time interrupt i rtii fff2, f3 irq (external pin) i none fff4, f5 xirq pin x none fff6, f7 software interrupt none none fff8, f9 illegal opcode trap none none fffa, fb cop failure none nocop fffc, fd clock monitor fail none cme fffe, ff reset none none
interrupts m68hc11e family data sheet, rev. 5.1 freescale semiconductor 89 end of the interrupt service routine, the return-from-interrupt instruction is executed and the saved registers are pulled from the stack in reverse order so that normal program execution can resume. refer to chapter 4 central processor unit (cpu) . 5.5.2 non-maskable in terrupt request (xirq ) non-maskable interrupts are useful because they ca n always interrupt cpu operations. the most common use for such an interrupt is for serious system problems, such as program runaway or power failure. the xirq input is an updated version of the nmi (non-maskable interrupt) input of earlier mcus. upon reset, both the x bit and i bit of the ccr ar e set to inhibit all maskable interrupts and xirq . after minimum system initialization, software can clea r the x bit by a tap instruction, enabling xirq interrupts. thereafter, software cannot set the x bit. thus, an xirq interrupt is a non-maskable interrupt. because the operation of the i-bit-related interrupt structure has no effect on the x bit, the internal xirq pin remains unmasked. in the interrupt priority logic, the xirq interrupt has a higher priority than any source that is maskable by the i bit. all i-bit-related interrupts oper ate normally with their own priority relationship. when an i-bit-related interrupt occurs, the i bit is automatically set by hardware after stacking the ccr byte. the x bit is not affected. when an x-bit-related interrupt occurs, both the x and i bits are automatically set by hardware after stacking the ccr. a return-from-interrupt instruction restores the x and i bits to their pre-interrupt request state. 5.5.3 illegal opcode trap because not all possible opcodes or opcode sequences are defined, t he mcu includes an illegal opcode detection circuit, which generates an interrupt request. when an illegal opcode is detected and the interrupt is recognized, the current value of the progr am counter is stacked. a fter interrupt service is complete, reinitialize the stack pointer so repeated execution of illegal opcodes does not cause stack underflow. left uninitialized, the illegal opcode vector can point to a memory location that contains an illegal opcode. this condition causes an infinite loop that causes stack underflow. the stack grows until the system crashes. the illegal opcode trap mechanism works for all uni mplemented opcodes on all four opcode map pages. the address stacked as the return address for the ille gal opcode interrupt is the address of the first byte of the illegal opcode. otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. the stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode. table 5-5. stacking order on entry to interrupts memory location cpu registers sp pcl sp?1 pch sp?2 iyl sp?3 iyh sp?4 ixl sp?5 ixh sp?6 acca sp?7 accb sp?8 ccr
resets and interrupts m68hc11e family data sheet, rev. 5.1 90 freescale semiconductor 5.5.4 software interrupt (swi) swi is an instruction, and thus cannot be interrupted until complete. swi is not inhibited by the global mask bits in the ccr. because execution of swi se ts the i mask bit, once an swi interrupt begins, other interrupts are inhibited until swi is complete, or until user software clears the i bit in the ccr. 5.5.5 maskable interrupts the maskable interrupt structure of the mcu can be extended to include additional external interrupt sources through the irq pin. the default configuration of this pin is a low-level sensitive wired-or network. when an event triggers an interrupt, a software accessible interrupt flag is set. when enabled, this flag causes a constant request fo r interrupt service. after the flag is cleared, the service request is released. 5.5.6 reset and interrupt processing figure 5-5 and figure 5-6 illustrate the reset and interrupt process. figure 5-5 illustrates how the cpu begins from a reset and how interrupt detection relates to normal opcode fetches. figure 5-6 is an expansion of a block in figure 5-5 and illustrates interrupt priorities. figure 5-7 shows the resolution of interrupt sources within the sci subsystem. 5.6 low-power operation both stop mode and wait mode suspend cpu operation until a reset or interrupt occurs. wait mode suspends processing and reduces power consumption to an intermediate level. stop mode turns off all on-chip clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire ram array. 5.6.1 wait mode the wai opcode places the mcu in wait mode, duri ng which the cpu registers are stacked and cpu processing is suspended until a qualified interrupt is detected. the interrupt can be an external irq , an xirq , or any of the internally generated interrupts, such as the timer or serial interrupts. the on-chip crystal oscillator remains active throughout the wait standby period. the reduction of power in the wait condition depend s on how many internal clock signals driving on-chip peripheral functions can be shut down. the cpu is al ways shut down during wait. while in the wait state, the address/data bus repeatedly runs read cycles to the address where the ccr contents were stacked. the mcu leaves the wait state when it senses any interrupt that has not been masked. the free-running timer system is shut down only if the i bit is set to 1 and the cop system is disabled by nocop being set to 1. several other systems also can be in a reduced power-consumption state depending on the state of software-controlled configuration control bits. power consumption by the analog-to-digital (a/d) converter is not affected sign ificantly by the wait condition. however, the a/d converter current can be eliminated by writing the adpu bit to 0. the spi system is enabled or disabled by the spe control bit. the sci transmitter is enabled or disabled by the te bit, and the sci receiver is enabled or disabled by the re bit. therefore, t he power consumption in wait is dependent on the particular application.
low-power operation m68hc11e family data sheet, rev. 5.1 freescale semiconductor 91 figure 5-5. processing flow out of reset (sheet 1 of 2) 2a bit x in y n xirq y n pin low? ccr = 1? begin instruction sequence 1a stack cpu registers set bits i and x fetch vector $fff4, $fff5 set bits s , i , and x reset mcu hardware power-on reset (por) external reset clock monitor fail (with cme = 1) cop watchdog timeout (with nocop = 0) delay 4064 e cycles load program counter with contents of $fffe, $ffff (vector fetch) load program counter with contents of $fffc, $fffd (vector fetch) load program counter with contents of $fffa, $fffb (vector fetch) highest priority lowest priority
resets and interrupts m68hc11e family data sheet, rev. 5.1 92 freescale semiconductor figure 5-5. processing flow out of reset (sheet 2 of 2) bit i in ccr = 1? 2a y n any i-bit interrupt y n pending? fetch opcode illegal opcode? y n wai y n instruction? swi instruction? y n rti instruction? y n execute this instruction stack cpu registers any n y interrupt pending? set bit i in ccr resolve interrupt priority and fetch vector for highest pending source stack cpu registers set bit i in ccr fetch vector $fff8, $fff9 stack cpu registers set bit i in ccr fetch vector $fff6, $fff7 restore cpu registers from stack 1a stack cpu registers see figure 5?2
low-power operation m68hc11e family data sheet, rev. 5.1 freescale semiconductor 93 figure 5-6. interrupt priority resolution (sheet 1 of 2) 2a begin set x bit in ccr fetch vector $fff4, fff5 x bit in ccr set ? yes no xirq pin low ? yes no highest priority interrupt ? yes no irq ? yes no fetch vector $fff2, fff3 fetch vector $fff0, fff1 rtii = 1 ? yes no real-time interrupt ? yes no fetch vector $ffee, ffef ic1i = 1 ? yes no timer ic1f ? yes no fetch vector $ffec, ffed ic2i = 1 ? yes no timer ic2f ? yes no fetch vector $ffea, ffeb ic3i = 1 ? yes no timer ic3f ? yes no fetch vector $ffe8, ffe9 oc1i = 1 ? yes no timer oc1f ? yes no 2b fetch vector
resets and interrupts m68hc11e family data sheet, rev. 5.1 94 freescale semiconductor figure 5-6. interrupt priority resolution (sheet 2 of 2) toi = 1? y n y n paovi = 1? paii = 1? y n spie = 1? y n y n flag y n y n flag flag y n flags y n paif = 1? spif = 1? or tof = 1? paovf = 1 fetch vector $ffde, $ffdf fetch vector $ffdc, $ffdd fetch vector $ffda, $ffdb fetch vector $ffd6, $ffd7 fetch vector $ffd8, $ffd9 oc2i = 1? y n y n oc3i = 1? oc4i = 1? y n i4/o5i = 1? y n flag y n y n flag flag y n flag y n oc4f = 1? i4/o5if = 1? oc2f = 1? oc3f = 1 fetch vector $ffe6, $ffe7 fetch vector $ffe4, $ffe5 fetch vector $ffe2, $ffe3 fetch vector $ffe0, $ffe1 modf = 1? interrupt? see figure 5?3 2a 2b end fetch vector $fff2, $fff3 sci
low-power operation m68hc11e family data sheet, rev. 5.1 freescale semiconductor 95 figure 5-7. interrupt source resolution within sci 5.6.2 stop mode executing the stop instruction while the s bit in the ccr is equal to 0 places t he mcu in stop mode. if the s bit is not 0, the stop opcode is treated as a no-op (nop). stop mode offers minimum power consumption because all clocks, incl uding the crystal oscillator, are stopped while in this mode. to exit stop and resume normal processing, a logic low level must be applied to one of the external interrupts (irq or xirq ) or to the reset pin. a pending edge-triggered irq can also bring the cpu out of stop. because all clocks are stopped in this mode, all intern al peripheral functions also stop. the data in the internal ram is retained as long as v dd power is maintained. the cpu state and i/o pin levels are static and are unchanged by stop. therefore, when an interrupt comes to restart the system, the mcu resumes processing as if there were no interruption. if reset is used to restart the system, a normal reset sequence results in which all i/o pins and functions ar e also restored to their initial states. to use the irq pin as a means of recovering from stop , the i bit in the ccr must be clear (irq not masked). the xirq pin can be used to wake up the mcu from stop regardless of the state of the x bit in the ccr, although the recovery sequence depends on the state of the x bit. if x is set to 0 (xirq not flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? valid sci request no valid sci request
resets and interrupts m68hc11e family data sheet, rev. 5.1 96 freescale semiconductor masked), the mcu starts up, beginning with the stacki ng sequence leading to norm al service of the xirq request. if x is set to 1 (xirq masked or inhibited), then processing continues with the instruction that immediately follows the stop instruction, and no xirq interrupt service is requested or pending. because the oscillator is stopped in stop mode, a restart delay ma y be imposed to allow oscillator stabilization upon leaving stop. if the internal oscillator is being used, this delay is required; however, if a stable external oscillator is being used, the dly cont rol bit can be used to bypass this startup delay. the dly control bit is set by reset and can be optionally cl eared during initialization. if the dly equal to 0 option is used to avoid startup delay on recovery from stop, then reset should not be used as the means of recovering from stop, as this causes dly to be se t again by reset, imposing the restart delay. this same delay also applies to power-on reset, regardless of the state of the dly control bit, but does not apply to a reset while the clocks are running.
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 97 chapter 6 parallel input/output (i/o) ports 6.1 introduction all m68hc11 e-series mcus have fi ve input/output (i/o) ports and up to 38 i/o lines, depending on the operating mode. refer to table 6-1 for a summary of the ports and their shared functions. port pin function is mode dependent. do not confuse pin function with the electrical state of the pin at reset. port pins are either driven to a specified logi c level or are configured as high-impedance inputs. i/o pins configured as high-impedance inputs have port data that is indeterminate. in port descriptions, an i indicates this condition. port pins that are driven to a known logic level during reset are shown with a value of either 1 or 0. some control bits are unaffected by reset. reset states for these bits are indicated with a u. table 6-1. input/output ports port input pins output pins bidirectional pins shared functions port a 3 3 2 timer port b ? 8 ? high-order address port c ? ? 8 low-order address and data bus port d ? ? 6 serial communications interface (sci) and serial peripheral interface (spi) port e 8 ? ? analog-to-digital (a/d) converter
parallel input/output (i/o) ports m68hc11e family data sheet, rev. 5.1 98 freescale semiconductor 6.2 port a port a shares functions with the timer system and has: three input-only pins three output-only pins two bidirectional i/o pins ddra7 ? data direction for port a bit 7 overridden if an output compare function is configured to control the pa7 pin 0 = input 1 = output the pulse accumulator uses port a bit 7 as the pai input, but the pin can also be used as general-purpose i/o or as an output compare. note even when port a bit 7 is configured as an output, the pin still drives the input to the pulse accumulator. paen ? pulse accumulator system enable bit refer to chapter 9 timing systems . pamod ? pulse accumulator mode bit refer to chapter 9 timing systems . pedge ? pulse accumulator edge control bit refer to chapter 9 timing systems . ddra3 ? data direction for port a bit 3 this bit is overridden if an output compare func tion is configured to control the pa3 pin. 0 = input 1 = output i4/o5 ? input capture 4/output compare 5 bit refer to chapter 9 timing systems . rtr[1:0] ? rti interrupt rate select bits refer to chapter 9 timing systems . address: $1000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset:i000iiii alternate function: pai oc2 oc3 oc4 ic4/oc5 ic1 ic2 ic3 and/or: oc1 oc1 oc1 oc1 oc1 ? ? ? i = indeterminate after reset figure 6-1. port a data register (porta) address: $1026 bit 7654321bit 0 read: ddra7 paewn pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 6-2. pulse accumulator control register (pactl)
port b m68hc11e family data sheet, rev. 5.1 freescale semiconductor 99 6.3 port b in single-chip or bootstrap modes, port b pins are general-purpose outputs. in expanded or special test modes, port b pins are high-order address outputs. 6.4 port c in single-chip and bootstrap modes, port c pins reset to high-impedance inputs. (ddrc bits are set to 0.) in expanded and special test modes, port c pins are multiplexed address/data bus and the port c register address is treated as an external memory location. address: $1004 bit 7654321bit 0 single-chip or bootstrap modes: read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset:00000000 expanded or special test modes: read: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 write: reset:00000000 figure 6-3. port b data register (portb) address: $1003 bit 7654321bit 0 single-chip or bootstrap modes: read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: indeterminate after reset expanded or special test modes: read: addr7 data7 addr6 data6 addr5 data5 addr4 data4 addr3 data3 addr2 data2 addr1 data1 addr0 data0 write: reset: indeterminate after reset figure 6-4. port c data register (portc) address: $1005 bit 7654321bit 0 read: pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 write: reset: indeterminate after reset figure 6-5. port c latched register (portcl)
parallel input/output (i/o) ports m68hc11e family data sheet, rev. 5.1 100 freescale semiconductor portcl is used in the handshake cl earing mechanism. when an active edge occurs on the stra pin, port c data is latched into the portcl register. reads of this register return the last value latched into portcl and clear staf flag (following a read of pioc with staf set). ddrc[7:0] ? port c data direction bits in the 3-state variation of output handshake mode, clear the corresponding ddrc bits. refer to figure 10-13. 3-state variation of output handshake timing diagram (stra enables output buffer) . 0 = input 1 = output 6.5 port d in all modes, port d bits [5:0] can be used either for general-purpose i/o or with the serial communications interface (sci) and serial peripheral interface (spi ) subsystems. during reset, port d pins pd[5:0] are configured as high-impedance inputs (ddrd bits cleared). bits [7:6] ? unimplemented always read 0 ddrd[5:0] ? port d data direction bits when ddrd bit 5 is 1 and mstr = 1 in spcr, pd5/ss is a general-purpose output and mode fault logic is disabled. 0 = input 1 = output address: $1007 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 6-6. port c data direction register (ddrc) address: $1008 bit 7654321bit 0 read: 0 0 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:??iiiiii alternate function: ? ? pd5 ss pd4 sck pd3 mosi pd2 miso pd1 tx pd0 rxd i = indeterminate after reset figure 6-7. port d data register (portd) address: $1009 bit 7654321bit 0 read: ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 = unimplemented figure 6-8. port d data direction register (ddrd)
port e m68hc11e family data sheet, rev. 5.1 freescale semiconductor 101 6.6 port e port e is used for general-purpose static inputs or pins that share functions with the analog-to-digital (a/d) converter system. when some port e pins are being used for general-purpose input and others are being used as a/d inputs, porte should not be read during the sample portion of an a/d conversion. 6.7 handshake protocol simple and full handshake input and output functions are available on ports b and c pins in single-chip mode. in simple strobed mode, port b is a strobed output port and port c is a latching input port. the two activities are available simultaneously. the strb output is pulsed for two e-clock periods eac h time there is a write to the portb register. the invb bit in the pioc register controls the polarity of strb pulses. port c levels are latched into the alternate port c latch (portcl) register on each as sertion of the stra input. stra edge select, flag, and interrupt enable bits are located in the pioc regi ster. any or all of the port c lines can still be used as general-purpose i/o while in strobed input mode. full handshake modes use port c pins and the st ra and strb lines. input and output handshake modes are supported, and output handshake mode has a 3- stated variation. stra is an edge-detecting input and strb is a handshake output. control and enable bits are located in the pioc register. in full input handshake mode, the mcu asserts strb to signal an external system that it is ready to latch data. port c logic levels are latched into portcl when the stra line is asserted by the external system. the mcu then negates strb. the mcu reasserts strb afte r the portcl register is read. in this mode, a mix of latched inputs, static inputs, and static outputs is allowed on port c, differentiated by the data direction bits and use of the portc and portcl registers. in full output handshake mode, the mcu writes data to portcl which, in turn, asserts the strb output to indicate that data is ready. the external system reads port c data and asserts the stra input to acknowledge that data has been received. in the 3-state variation of output handshake mode, lines intended as 3-state handshake outputs are configured as inputs by clearing the corresponding ddrc bits. the mcu writes data to portcl and asserts strb. the external system responds by activating the stra input, which forces the mcu to drive the data in portc out on all of the port c lines. afte r the trailing edge of the active signal on stra, the mcu negates the strb signal. the 3-state mode variation does not allow part of port c to be used for static inputs while other port c pins are being used for handshake outputs. refer to the 6.8 parallel i/o control register for further information. address: $100a bit 7654321bit 0 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: indeterminate after reset alternate function: an7 an6 an5 an4 an3 an2 an1 an0 figure 6-9. port e data register (porte)
parallel input/output (i/o) ports m68hc11e family data sheet, rev. 5.1 102 freescale semiconductor 6.8 parallel i/o control register the parallel handshake functions are available only in the single-chip operating mode. pioc is a read/write register except for bit 7, which is read only. table 6-2 shows a summary of handshake operations. staf ? strobe a interrupt status flag staf is set when the selected edge occurs on strobe a. this bit can be cleared by a read of pioc with staf set followed by a read of portcl (simple strobed or full input handshake mode) or a write to portcl (output handshake mode). 0 = no edge on strobe a 1 = selected edge on strobe a stai ? strobe a interrupt enable mask bit 0 = staf does not request interrupt 1 = staf requests interrupt table 6-2. parallel i/o control staf clearing sequence hnds oin pls ega port b port c simple strobed mode read pioc with staf = 1 then read portcl 0x x inputs latched into portcl on any active edge on stra strb pulses on writes to portb full-input hand- shake mode read pioc with staf = 1 then read portcl 10 0 = strb active level 1 = strb active pulse inputs latched into portcl on any active edge on stra normal output port, unaffected in handshake modes full- output hand- shake mode read pioc with staf = 1 then write portcl 11 0 = strb active level 1 = strb active pulse driven as outputs if stra at active level; follows ddrc if stra not at active level normal output port, unaffected in handshake modes address: $1002 bit 7654321bit 0 read: staf stai cwom hnds oin pls ega invb write: reset:00000u11 u = unaffected figure 6-10. parallel i/o control register (pioc) 1 0 0 1 0 1 port c driven stra active edge follow ddrc follow ddrc
parallel i/o control register m68hc11e family data sheet, rev. 5.1 freescale semiconductor 103 cwom ? port c wired-or mode bit (affects all eight port c pins) it is customary to have an external pullup resistor on lines that are driven by open-drain devices. 0 = port c outputs are normal cmos outputs. 1 = port c outputs are open-drain outputs. hnds ? handshake mode bit 0 = simple strobe mode 1 = full input or output handshake mode oin ? output or input handshake select bit hnds must be set to 1 for this bit to have meaning. 0 = input handshake 1 = output handshake pls ? pulsed/interlocked handshake operation bit hnds must be set to 1 for this bit to have meani ng. when interlocked handshak e is selected, strobe b is active until the selected edge of strobe a is detected. 0 = interlocked handshake 1 = pulsed handshake (strobe b pulses high for two e-clock cycles.) ega ? active edge for strobe a bit 0 = stra falling edge selected, high level ac tivates port c outputs (output handshake) 1 = stra rising edge selected, low level activates port c outputs (output handshake) invb ? invert strobe b bit 0 = active level is logic 0. 1 = active level is logic 1.
parallel input/output (i/o) ports m68hc11e family data sheet, rev. 5.1 104 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 105 chapter 7 serial communications interface (sci) 7.1 introduction the serial communications interface (sci) is a un iversal asynchronous receiver transmitter (uart), one of two independent serial input/output (i/o) subsystems in the m68hc11 e series of microcontrollers. it has a standard non-return-to-zero (nrz) format (one start bit , eight or nine data bits, and one stop bit). several baud rates are available. the sci transmitte r and receiver are independent, but use the same data format and bit rate. all members of the e series contain the same sci, with one exception. the sci system in the mc68hc11e20 and mc68hc711e20 mcus have an e nhanced sci baud rate generator. a divide-by-39 stage has been added that is enabled by an extra bit in the baud register. this increases the available sci baud rate selections. refer to figure 7-8 and 7.7.5 baud rate register . 7.2 data format the serial data format requires these conditions: 1. an idle line in the high state before transmission or reception of a message 2. a start bit, logic 0, transmitted or received , that indicates the start of each character 3. data that is transmitted and received least significant bit (lsb) first 4. a stop bit, logic 1, used to indicate the end of a fr ame. a frame consists of a start bit, a character of eight or nine data bits, and a stop bit. 5. a break, defined as the transmission or reception of a logic 0 for some multiple number of frames selection of the word length is controlled by the m bit of sci control register (sccr1). 7.3 transmit operation the sci transmitter includes a parallel transmit data register (scdr) and a serial shift register. the contents of the serial shift register can be writt en only through the scdr. this double buffered operation allows a character to be shifted out serially while another char acter is waiting in the scdr to be transferred into the serial shift register. the output of the serial shift register is applied to txd as long as transmission is in progress or the transmit enable (te) bit of serial communication control register 2 (sccr2) is set. the block diagram, figure 7-1 , shows the transmit serial shift regist er and the buffer logic at the top of the figure.
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 106 freescale semiconductor figure 7-1. sci transmitter block diagram fe nf or idle rdrf tc tdre scsr interrupt status sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd scdr tx buffer transfer tx buffer shift enable jam enable preamble?jam 1s break?jam 0s write only force pin direction (out) size 8/9 wake m t8 r8 sccr1 sci control 1 transmitter baud rate clock 8 8 8 see note note: refer to figure b-1. evbu schematic diagram for an example of connecting txd to a pc.
receive operation m68hc11e family data sheet, rev. 5.1 freescale semiconductor 107 7.4 receive operation during receive operations, the transmit sequence is reve rsed. the serial shift register receives data and transfers it to a parallel receive data register (scdr) as a complete word. this double buffered operation allows a character to be shifted in serially while another character is already in the scdr. an advanced data recovery scheme distin guishes valid data from noise in the se rial data stream. the data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. see figure 7-2 . 7.5 wakeup feature the wakeup feature reduces sci service overhead in multiple receiver systems. software for each receiver evaluates the first characte r of each message. the receiver is placed in wakeup mode by writing a 1 to the rwu bit in the sccr2 regi ster. while rwu is 1, all of the receiver-related status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot beco me set). although rwu can be cleared by a software write to sccr2, to do so would be unusual. normally, rwu is set by software and is cleared automatically with hardware. whenever a new mess age begins, logic alerts the sleeping receivers to wake up and evaluate the initial character of the new message. two methods of wakeup are available: idle-line wakeup address-mark wakeup during idle-line wakeup, a sleeping receiver awakens as soon as t he rxd line becomes idle. in the address-mark wakeup, logic 1 in the most signific ant bit (msb) of a character wakes up all sleeping receivers. 7.5.1 idle-line wakeup to use the receiver wakeup method, establish a software addressing scheme to allow the transmitting devices to direct a message to indivi dual receivers or to groups of re ceivers. this addressing scheme can take any form as long as all transmitting and rece iving devices are programmed to understand the same scheme. because the addressing inform ation is usually the first frame(s) in a message, receivers that are not part of the current task do not become burdened with the entire set of addressing frames. all receivers are awake (rwu = 0) when each message begins. as soon as a receiver determines that the message is not intended for it, software sets the rwu bit (rwu = 1), which inhibits further flag setting until the rxd line goes idle at the end of the message. as soon as an idle line is detected by receiver logic, hardware automatically clears the rwu bit so that the first frame of the next message can be received. this type of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time between frames in a message.
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 108 freescale semiconductor figure 7-2. sci receiver block diagram fe nf or idle rdrf tc tdre scsr sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m t8 r8 wakeup logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0 rxd scdr rx buffer stop (8)76543210 10 (11) - bit rx shift register read only sccr1 sci control 1 rie rdrf start msb all 1s data recovery 16 rwu re m disable driver receiver baud rate clock 8 8 8 see note note: refer to figure b-1. evbu schematic diagram for an example of connecting rxd to a pc.
sci error detection m68hc11e family data sheet, rev. 5.1 freescale semiconductor 109 7.5.2 address-mark wakeup the serial characters in this type of wakeup consist of seven (eight if m = 1) information bits and an msb, which indicates an address character (when set to 1, or mark). the first character of each message is an addressing character (msb = 1). all receivers in the system evaluate this character to determine if the remainder of the message is directed toward this par ticular receiver. as soon as a receiver determines that a message is not intended for it, the receiver activates the rwu function by using a software write to set the rwu bit. because setting rwu inhibits rece iver-related flags, there is no further software overhead for the rest of this message. when the next message begins, its first character has its msb set, which automatically clears the rwu bit and enables normal character reception. the first c haracter whose msb is set is also the first character to be received after wakeup because rwu gets cleared be fore the stop bit for that frame is serially received. this type of wakeup allows messages to in clude gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. 7.6 sci error detection three error conditions ? scdr overrun, received bi t noise, and framing ? can occur during generation of sci system interrupts. three bits (or, nf, and fe) in the serial communications status register (scsr) indicate if one of these error conditions exists. the overrun error (or) bit is set when the next byte is ready to be transferred from the receive shift register to the scdr and the scdr is already full ( rdrf bit is set). when an overrun error occurs, the data that caused the overrun is lost and the data that was already in scdr is not disturbed. the or is cleared when the scsr is read (with or set), followed by a read of the scdr. the noise flag (nf) bit is set if there is noise on any of the received bits, including the start and stop bits. the nf bit is not set until the rdrf flag is set. the nf bit is cleared when the scsr is read (with fe equal to 1) followed by a read of the scdr. when no stop bit is detected in the received data character, the framing error (fe) bit is set. fe is set at the same time as the rdrf. if the byte received ca uses both framing and overrun errors, the processor only recognizes the overrun error. the framing error flag inhibits furt her transfer of data into the scdr until it is cleared. the fe bit is cleared when the scsr is read (with fe equal to 1) followed by a read of the scdr. 7.7 sci registers five addressable registers are associated with the sci: four control and status registers: ? serial communications control register 1 (sccr1) ? serial communications control register 2 (sccr2) ? baud rate register (baud) ? serial communications status register (scsr) one data register: ? serial communications data register (scdr) the sci registers are the same for all m68hc11 e-se ries devices with one exception. the sci system for mc68hc(7)11e20 contains an extra bit in the baud register that provides a greater selection of baud prescaler rates. refer to 7.7.5 baud rate register , figure 7-8 , and figure 7-9 .
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 110 freescale semiconductor 7.7.1 serial communic ations data register scdr is a parallel register that performs two functions: the receive data register when it is read the transmit data register when it is written reads access the receive data buffer and writes ac cess the transmit data buffer. receive and transmit are double buffered. 7.7.2 serial communicat ions control register 1 the sccr1 register provides the control bits that determine word length and select the method used for the wakeup feature. r8 ? receive data bit 8 if m bit is set, r8 stores the ninth bit in the receive data character. t8 ? transmit data bit 8 if m bit is set, t8 stores the ninth bit in the transmit data character. bit 5 ? unimplemented always reads 0 m ? mode bit (select character format) 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ? wakeup by address mark/idle bit 0 = wakeup by idle line recognition 1 = wakeup by address mark (most significant data bit set) bits [2:0] ? unimplemented always read 0 address: $102f bit 7654321bit 0 read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: indeterminate after reset figure 7-3. serial communications data register (scdr) address: $102c bit 7654321bit 0 read: r8 t8 m wake write: reset:i i 000000 i = indeterminate after reset = unimplemented figure 7-4. serial communications control register 1 (sccr1)
sci registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 111 7.7.3 serial communicat ions control register 2 the sccr2 register provides the control bits that enable or disable individual sci functions. tie ? transmit interrupt enable bit 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ? transmit complete interrupt enable bit 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ? receiver interrupt enable bit 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ? idle-line interrupt enable bit 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ? transmitter enable bit when te goes from 0 to 1, one unit of idle c haracter time (logic 1) is queued as a preamble. 0 = transmitter disabled 1 = transmitter enabled re ? receiver enable bit 0 = receiver disabled 1 = receiver enabled rwu ? receiver wakeup control bit 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ? send break at least one character time of break is queued and sent each time sbk is written to 1. as long as the sbk bit is set, break characters are queued and s ent. more than one break may be sent if the transmitter is idle at the time the sbk bit is togg led on and off, as the baud ra te clock edge could occur between writing the 1 and writing the 0 to sbk. 0 = break generator off 1 = break codes generated address: $102d bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 7-5. serial communications control register 2 (sccr2)
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 112 freescale semiconductor 7.7.4 serial communic ation status register the scsr provides inputs to the interrupt logic ci rcuits for generation of the sci system interrupt. tdre ? transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr with tdre set and then writing to scdr. 0 = scdr busy 0 = scdr empty tc ? transmit complete flag this flag is set when the transmitter is idle (no dat a, preamble, or break transmission in progress). clear the tc flag by reading scsr with tc set and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ? receive data register full flag this flag is set if a received char acter is ready to be read from s cdr. clear the rdrf flag by reading scsr with rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle ? idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is in hibited when rwu = 1. clear idle by reading scsr with idle set and then reading scdr. 0 = rxd line active 1 = rxd line idle or ? overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr with or set and then reading scdr. 0 = no overrun 1 = overrun detected nf ? noise error flag nf is set if majority sample logic detects any thing other than a unanimous decision. clear nf by reading scsr with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected address: $102e bit 7654321bit 0 read: tdre tc rdrf idle or nf fe write: reset:11000000 = unimplemented figure 7-6. serial communications status register (scsr)
sci registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 113 fe ? framing error flag fe is set when a 0 is detected where a stop bit was expected. clear the fe flag by reading scsr with fe set and then reading scdr. 0 = stop bit detected 1 = zero detected bit 0 ? unimplemented always reads 0 7.7.5 baud rate register use this register to select different baud rate s for the sci system. the scp[1:0] (scp[2:0] in mc68hc(7)11e20) bits function as a prescaler for the scr[2:0] bits. together, these five bits provide multiple baud rate combinations for a given crystal fr equency. normally, this register is written once during initialization. the prescaler is set to its fastest rate by default out of reset and can be changed at any time. refer to table 7-1 for normal baud rate selections. tclr ? clear baud rate counter bit (test) scp[2:0] ? sci baud rate prescaler select bits note scp2 applies to mc68hc(7)11e20 only. when scp2 = 1, scp[1:0] must equal 0s. any other values for scp[1:0] are not decoded in the prescaler and the results are unpredictable. refer to figure 7-8 and figure 7-9 . rckb ? sci baud rate clock check bit (test) see table 7-1 . address: $102b bit 7654321bit 0 read: tclr scp2 scp1 scp0 rckb scr2 scr1 scr0 write: reset:00000uuu u = unaffected figure 7-7. baud rate register (baud)
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 114 freescale semiconductor table 7-1. baud rate values prescale divide baud set divide crystal frequency (mhz) 4.00 4.9152 8.00 10.00 12.00 16.00 prescaler selects bus frequency (mhz) scp2 scp1 scp0 scr2 scr1 scr0 1.00 1.23 2.00 2.50 3.00 4.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 2 4 8 16 32 64 128 62500 31250 15625 7813 3906 1953 977 488 76800 38400 19200 9600 4800 2400 1200 600 125000 62500 31250 15625 7813 3906 1953 977 156250 78125 39063 19531 9766 4883 2441 1221 187500 93750 46875 23438 11719 5859 2930 1465 250000 125000 62500 31250 15625 7813 3906 1953 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 3 3 3 3 3 3 3 1 2 4 8 16 32 64 128 20833 10417 5208 2604 1302 651 326 163 25600 12800 6400 3200 1600 800 400 200 41667 20833 10417 5208 2604 1302 651 326 52083 26042 13021 6510 3255 1628 814 407 62500 31250 15625 7813 3906 1953 977 488 83333 41667 20833 10417 5208 2604 1302 651 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4 4 4 4 4 4 4 4 1 2 4 8 16 32 64 128 15625 7813 3906 1953 977 488 244 122 19200 9600 4800 2400 1200 600 300 150 31250 15625 7813 3906 1953 977 488 244 39063 19531 9766 4883 2441 1221 610 305 46875 23438 11719 5859 2930 1465 732 366 62500 31250 15625 7813 3906 1953 977 488 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 13 13 13 13 13 13 13 13 1 2 4 8 16 32 64 128 4808 2404 1202 601 300 150 75 38 5908 2954 1477 738 369 185 92 46 9615 4808 2404 1202 601 300 150 75 12019 6010 3005 1502 751 376 188 94 14423 7212 3606 1803 901 451 225 113 19231 9615 4808 2404 1202 601 300 150 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 39 39 39 39 39 39 39 39 1 2 4 8 16 32 64 128 1603 801 401 200 100 50 25 13 1969 985 492 246 123 62 31 15 3205 1603 801 401 200 100 50 25 4006 2003 1002 501 250 125 63 31 4808 2404 1202 601 300 150 75 38 6410 3205 1603 801 401 200 100 50 shaded areas reflect standard baud rates. on mc68hc(7)11e20 do not set scp1 or scp0 when scp2 is 1.
sci registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 115 scr[2:0] ? sci baud rate select bits selects receiver and transmitter bit rate based on output from baud rate prescaler stage. refer to figure 7-8 and figure 7-9 . the prescaler bits, scp[2:0], determine the highest baud rate, and the scr[2:0] bits select an additional binary submultiple ( 1, 2, 4, through 128) of this highest baud rate. the result of these two dividers in series is the 16x receiver baud rate clock. the scr[2:0] bits are not affected by reset and can be changed at any time, although they s hould not be changed when any sci transfer is in progress. figure 7-8 and figure 7-9 illustrate the sci baud rate timing chai n. the prescaler select bits determine the highest baud rate. the rate select bits determine additional divide by two stages to arrive at the receiver timing (rt) clock rate. the baud rate clo ck is the result of dividing the rt clock by 16. figure 7-8. sci baud rate generator block diagram 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 sci transmit baud rate (1x) sci receive baud rate (16x) 16 1:1:1 scr[2:0] 3 0:0 4 13 0:1 1:0 1:1 oscillator and clock generator ( 4) scp[1:0] internal bus clock (ph2) e as extal xtal
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 116 freescale semiconductor figure 7-9. mc68hc(7)11e20 sci baud rate generator block diagram 7.8 status flags and interrupts the sci transmitter has two status flags. these status flags can be read by software (polled) to tell when the corresponding condition exists. alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt reque sts when the corresponding condition is present. status flags are automatically set by hardware logi c conditions, but must be cleared by software, which provides an interlock mechanism that enables logic to know when software has noticed the status indication. the software clearing sequence for these flags is automatic. functi ons that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 sci transmit baud rate (1x) sci receive baud rate (16x) 16 1:1:1 scr[2:0] 3 0:0:0 4 13 0:0:1 0:1:0 0:1:1 oscillator and clock generator ( 4) scp[2:0]* internal bus clock (ph2) e as extal xtal 39 1:0:0 *scp2 is present only on mc68hc(7)11e20.
receiver flags m68hc11e family data sheet, rev. 5.1 freescale semiconductor 117 tdre and tc flags are normally set when the transmi tter is first enabled (te set to 1). the tdre flag indicates there is room in the transmit queue to store another data character in the tdr. the tie bit is the local interrupt mask for tdre. when tie is 0, tdre must be polled. when tie and tdre are 1, an interrupt is requested. the tc flag indicates the transmitter has completed the queue. the tcie bit is the local interrupt mask for tc. when tcie is 0, tc must be polled. when tcie is 1 and tc is 1, an interrupt is requested. writing a 0 to te requests that the transmitter stop when it can. the transmitter completes any transmission in progress before actually shutting dow n. only an mcu reset can cause the transmitter to stop and shut down immediately. if te is written to 0 when the transmitter is already idle, the pin reverts to its general-purpose i/o function (synchronized to the bit-rate clock). if anything is being transmitted when te is written to 0, that character is complet ed before the pin reverts to general-purpose i/o, but any other characters waiting in the transmit queue are los t. the tc and tdre flags are set at the completion of this last character, even though te has been disabled. 7.9 receiver flags the sci receiver has five status flags, three of which can generate interrupt requests. the status flags are set by the sci logic in response to specific cond itions in the receiver. thes e flags can be read (polled) at any time by software. refer to figure 7-10 , which shows sci interrupt arbitration. when an overrun takes place, the new character is lost, and the character that was in its way in the parallel rdr is undisturbed. rdrf is set when a character has been received and transferred into the parallel rdr. the or flag is set instead of rdrf if overrun occurs. a new c haracter is ready to be transferred into rdr before a previous character is read from rdr. the nf and fe flags provide addi tional information about the character in the rdr, but do not generate interrupt requests. the last receiver status flag and interrupt source come from the idle flag. the rx d line is idle if it has constantly been at logic 1 for a full character time. the idle flag is set only after the rxd line has been busy and becomes idle, which prevents repeated interrupts for the whole time rxd remains idle.
serial communications interface (sci) m68hc11e family data sheet, rev. 5.1 118 freescale semiconductor figure 7-10. interrupt source resolution within sci flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? valid sci request no valid sci request
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 119 chapter 8 serial peripheral interface (spi) 8.1 introduction the serial peripheral interface (spi), an independent serial communications subsystem, allows the mcu to communicate synchronously with peripheral devices, such as: frequency synthesizers liquid crystal display (lcd) drivers analog-to-digital (a/d) converter subsystems other microprocessors the spi is also capable of inter-processor communica tion in a multiple master system. the spi system can be configured as either a master or a slave devi ce. when configured as a master, data transfer rates can be as high as one-half the e-clock rate (1.5 mbits per second for a 3-mhz bus frequency). when configured as a slave, data transfers can be as fast as the e-clock rate (3 mbits per second for a 3-mhz bus frequency). 8.2 functional description the central element in the spi system is the block c ontaining the shift register and the read data buffer. the system is single buffered in the transmit direction and double buffered in the receive direction. this means that new data for transmissi on cannot be written to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. as long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occu rs. a single mcu register address is used for reading data from the read data buffer and for writing data to the shifter. the spi status block represents the spi status func tions (transfer complete, write collision, and mode fault) performed by the serial peri pheral status register (spsr). the spi control block represents those functions that control the spi system through t he serial peripheral control register (spcr). refer to figure 8-1 , which shows the spi block diagram. 8.3 spi transfer formats during an spi transfer, data is simultaneously transmi tted and received. a serial clock line synchronizes shifting and sampling of the information on the two seri al data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the select line can opti onally be used to indicate a multiple master bus contention. refer to figure 8-2 .
serial peripheral interface (spi) m68hc11e family data sheet, rev. 5.1 120 freescale semiconductor figure 8-1. spi block diagram 8.4 clock phase and polarity controls software can select one of four combinations of seri al clock phase and polarity using two bits in the spi control register (spcr). the clock polarity is specif ied by the cpol control bit, which selects an active high or active low clock, and has no significant effect on the transfer format. the clock phase (cpha) control bit selects one of two different transfer form ats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. when cpha equals 0, the ss line must be negated and reasserted bet ween each successive serial byte. also, if the slave writes data to the spi data register (spdr) while ss is low, a write collision error results. when cpha equals 1, the ss line can remain low between successive transfers. 8--bit shift register read data buffer msb lsb miso pd2 mosi pd3 sck pd4 ss pd5 divider 2 4 16 3 2 internal mcu clock select s m m s s m pin control logic clock logic clock spif spe dwom instr cpol cpha spri spro spi control register mstd sec dwom spri spro mstr spe spi control spif wcol mode spi status register spi interrupt request internal data bus
spi signals m68hc11e family data sheet, rev. 5.1 freescale semiconductor 121 figure 8-2. spi transfer format 8.5 spi signals this subsection contai ns descriptions of the four spi signals: master in/slave out (miso) master out/slave in (mosi) serial clock (sck) slave select (ss ) any spi output line must have its corresponding data direction bit in ddrd register set. if the ddr bit is clear, that line is disconnected from the spi logic and becomes a general-purpose input. all spi input lines are forced to act as inputs regardless of the stat e of the corresponding ddr bits in ddrd register. 8.5.1 master in/slave out miso is one of two unidirectional se rial data signals. it is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. 8.5.2 master out/slave in the mosi line is the second of the two unidirectional serial data signal s. it is an output from a master device and an input to a slave device. the master dev ice places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb 1 2 3 5 4 slave cpha = 1 transfer in progress master transfer in progress slave cpha = 0 transfer in progress 1. ss asserted 2. master writes to spdr 3. first sck edge 4. spif set 5. ss negated sample input data out (cpha = 0) sample input data out (cpha = 1)
serial peripheral interface (spi) m68hc11e family data sheet, rev. 5.1 122 freescale semiconductor 8.5.3 serial clock sck, an input to a slave device, is generated by t he master device and synchronizes data movement in and out of the device through the mosi and miso lines. master and slave devices are capable of exchanging a byte of information dur ing a sequence of eight clock cycles. four possible timing relationships can be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the spi clock rate select bits, spr[1 :0], in the spcr of the master device, select the clock rate. in a slave device, spr[1:0] have no effect on the operation of the spi. 8.5.4 slave select the slave select (ss ) input of a slave device must be externa lly asserted before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. if it goes lo w, a mode fault error flag (modf) is set in the serial peripheral status register (spsr ). to disable the mode fault circuit, write a 1 in bit 5 of the port d data direction register. this sets the ss pin to act as a general-purpose output rather than the dedicated input to the slave select circuit, thus inhibiting t he mode fault flag. the other three lines are dedicated to the spi whenever the serial peripheral interface is on. the state of the master and slave cpha bits affects the operation of ss . cpha settings should be identical for master and slave. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss can be left low between successive spi characters. in cases where there is only one spi slave mcu, its ss line can be tied to v ss as long as only cpha = 1 clock mode is used. 8.6 spi system errors two system errors can be detected by the spi system. the first type of error arises in a multiple-master system when more than one spi device simultaneously tries to be a master. this error is called a mode fault. the second type of error, write collision, indicates that an attempt was made to write data to the spdr while a transfer was in progress. when the spi system is configured as a master and the ss input line goes to active low, a mode fault error has occurred ? usually because two devices have a ttempted to act as master at the same time. in cases where more than one device is concurrently co nfigured as a master, there is a chance of contention between two pin drivers. for push-pull cmos drivers, this contention can cause permanent damage. the mode fault mechanism attempts to prot ect the device by disabling the driv ers. the mstr control bit in the spcr and all four ddrd control bits associated with the spi are cleared and an interrupt is generated subject to masking by the spie control bit and the i bit in the ccr. other precautions may need to be taken to prevent driver damage. if two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. the amount of damage possible depends on the length of time both devices attempt to act as master. a write collision error occurs if the spdr is written while a transfer is in progress. because the spdr is not double buffered in the transmit direction, writes to spdr cause data to be written directly into the spi shift register. because this write corrupts any transfer in progress, a write collision error is generated. the transfer continues undisturbed, and the write data that caused the error is not written to the shifter.
spi registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 123 a write collision is normally a slave error because a sl ave has no control over when a master initiates a transfer. a master knows when a transfer is in progre ss, so there is no reason for a master to generate a write-collision error, although the sp i logic can detect write collisions in both master and slave devices. the spi configuration determines the characteristics of a transfer in progress. for a master, a transfer begins when data is written to spdr and ends when spi f is set. for a slave with cpha equal to 0, a transfer starts when ss goes low and ends when ss returns high. in this case, spif is set at the middle of the eighth sck cycle when data is transferred from the shifter to the parallel data register, but the transfer is still in progress until ss goes high. for a slave with cpha equal to 1, transfer begins when the sck line goes to its active level, which is the edge at the beginning of the first sck cycle. the transfer ends in a slave in which cpha equals 1 when spif is set. 8.7 spi registers the three spi registers are: serial peripheral control register (spcr) serial peripheral status register (spsr) serial peripheral data register (spdr) these registers provide control, status, and data storage functions. 8.7.1 serial perip heral control register spie ? serial peripheral interrupt enable bit set the spe bit to 1 to request a hardware interrupt sequence each time the spif or modf status flag is set. spi interrupts are inhibited if this bit is clear or if the i bit in the condition code register is 1. 0 = spi system interrupts disabled 1 = spi system interrupts enabled spe ? serial peripheral system enable bit when the spe bit is set, the port d bit 2, 3, 4, and 5 pins are dedicated to the spi function. if the spi is in the master mode and ddrd bit 5 is set, then the port d bit 5 pin becomes a general-purpose output instead of the ss input. 0 = spi system disabled 1 = spi system enabled dwom ? port d wired-or mode bit dwom affects all port d pins. 0 = normal cmos outputs 1 = open-drain outputs address: $1028 bit 7654321bit 0 read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu u = unaffected figure 8-3. serial peripheral control register (spcr)
serial peripheral interface (spi) m68hc11e family data sheet, rev. 5.1 124 freescale semiconductor mstr ? master mode select bit it is customary to have an external pullup resistor on lines that are driven by open-drain devices. 0 = slave mode 1 = master mode cpol ? clock polarity bit when the clock polarity bit is cleared and data is not being transferred, the sck pin of the master device has a steady state low value. when cpol is set, sck idles high. refer to figure 8-2 and 8.4 clock phase and polarity controls . cpha ? clock phase bit the clock phase bit, in conjunction wi th the cpol bit, controls the clock-data relationship between master and slave. the cpha bit selects one of two different clocking protocols. refer to figure 8-2 and 8.4 clock phase and polarity controls . spr[1:0] ? spi clock rate select bits these two bits select the spi clock (sck) rate when the device is configured as master. when the device is configured as slave, t hese bits have no effect. refer to table 8-1 . 8.7.2 serial perip heral status register spif ? spi interrupt complete flag spif is set upon completion of data transfer between the processor and the external device. if spif goes high, and if spie is set, a serial peripheral interrupt is generated. to clear the spif bit, read the spsr with spif set, then access the spdr. unless sp sr is read (with spif se t) first, attempts to write spdr are inhibited. wcol ? write collision bit clearing the wcol bit is accomplished by reading t he spsr (with wcol set) followed by an access of spdr. refer to 8.5.4 slave select and 8.6 spi system errors . 0 = no write collision 1 = write collision table 8-1. spi clock rates spr[1:0] divide e clock by frequency at e = 1 mhz (baud) frequency at e = 2 mhz (baud) frequency at e = 3 mhz ( baud) frequency at e = 4 mhz (baud) 0 0 2 500 khz 1.0 mhz 1.5 mhz 2 mhz 0 1 4 250 khz 500 khz 750 khz 1 mhz 1 0 16 62.5 khz 125 khz 187.5 khz 250 khz 1 1 32 31.3 khz 62.5 khz 93.8 khz 125 khz address: $1029 bit 7654321bit 0 read: spif wcol modf write: reset:00000000 = unimplemented figure 8-4. serial peripheral status register (spsr)
spi registers m68hc11e family data sheet, rev. 5.1 freescale semiconductor 125 bit 5 ? unimplemented always reads 0 modf ? mode fault bit to clear the modf bit, read the spsr (with mo df set), then write to the spcr. refer to 8.5.4 slave select and 8.6 spi system errors . 0 = no mode fault 1 = mode fault bits [3:0] ? unimplemented always read 0 8.7.3 serial peripheral data i/o register the spdr is used when transmitting or receiving data on the serial bus. only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. at the completion of transferring a byte of data, the spif status bi t is set in both the master and slave devices. a read of the spdr is actually a read of a buffer. to prevent an overrun and the loss of the byte that caused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. spi is double buffered in and single buffered out. address: $102a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 8-5. serial peripheral data i/o register (spdr)
serial peripheral interface (spi) m68hc11e family data sheet, rev. 5.1 126 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 127 chapter 9 timing systems 9.1 introduction the m68hc11 timing system is composed of five cl ock divider chains. the main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. the main timer?s programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. two prescaler control bits select the prescale rate. the prescaler output divides the system clock by 1, 4, 8, or 16. taps off of this main clocking chain drive circuitry that generates the slower clocks used by the pulse accumulator, the real-time interrupt (rti), and the computer operating properly (cop) watchdog subsyste ms, also described in this section. refer to figure 9-1 . all main timer system activities are referenced to this free-running counter. the counter begins incrementing from $0000 as the mcu comes out of reset and continues to the maximum count, $ffff. at the maximum count, the counter rolls over to $0000, sets an overflow flag, and continues to increment. as long as the mcu is running in a normal operating mode, there is no way to reset, change, or interrupt the counting. the capture/compare subsystem featur es three input capture channels, four output compare channels, and one channel that can be selected to perform either input capture or output compare. each of the three input capture functions ha s its own 16-bit input capture register (time capture latch) and each of the output compare functions has its own 16-bit compare register. all timer functions, including the timer overflow and rt i, have their own interrupt controls and separate interrupt vectors. the pulse accumulator contains an 8-bit counter and edge select logic. the pulse accumulator can operate in either event counting mode or gated ti me accumulation mode. during event counting mode, the pulse accumulator?s 8-bit counter increments w hen a specified edge is detected on an input signal. during gated time accumulation mode, an internal cl ock source increments the 8-bit counter while an input signal has a predetermined logic level. the real-time interrupt (rti) is a programmable periodi c interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates. the cop watchdog clock input (e 2 15 ) is tapped off of the free-running counter chain. the cop automatically times out unless it is serviced within a specific time by a program reset sequence. if the cop is allowed to time out, a reset is generated, which drives the reset pin low to reset the mcu and the external system. refer to table 9-1 for crystal-related frequencies and periods.
timing systems m68hc11e family data sheet, rev. 5.1 128 freescale semiconductor figure 9-1. timer clock divider chains e series tim div chain oscillator and clock generator as e clock spi sci receiver clock sci transmit clock e 2 6 pulse accumulator tcnt tof real-time interrupt e 2 13 4 e 2 15 r q q s r q q s force cop reset system reset clear cop timer ff2 ff1 (divide by four) internal bus clock (ph2) ic/oc 16 cr[1:0] prescaler ( 1, 4, 16, 64) prescaler ( 2, 4, 16, 32) spr[1:0] prescaler ( 1, 3, 4, 13) scp[1:0] prescaler ( 1, 2, 4, 8) rtr[1:0] prescaler ( 1, 2, 4,....128) scr[2:0] prescaler ( 1, 4, 8, 16) pr[1:0] 39 scp2 * * scp2 present on mc68hc(7)11e20 only
timer structure m68hc11e family data sheet, rev. 5.1 freescale semiconductor 129 9.2 timer structure figure 9-2 shows the capture/compare system block diagram. the port a pin control block includes logic for timer functions and for general-purpose i/o. for pi ns pa3, pa2, pa1, and pa0, this block contains both the edge-detection logic and the control logic th at enables the selection of which edge triggers an input capture. the digital level on pa[3:0] can be read at any time (read porta register), even if the pin is being used for the input capture f unction. pins pa[6:3] are used for either general-purpose i/o, or as output compare pins. when one of these pins is be ing used for an output compare function, it cannot be written directly as if it were a general-purpose out put. each of the output compare functions (oc[5:2]) is related to one of the port a output pins. output com pare one (oc1) has extra cont rol logic, allowing it optional control of any combination of the pa[7:3] pins. the pa7 pin can be used as a general-purpose i/o pin, as an input to the pulse ac cumulator, or as an oc1 output pin. 9.3 input capture the input capture function records the time an exte rnal event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. software can store latched values and use them to compute the pe riodicity and duration of events. for example, by storing the times of successive edges of an incomi ng signal, software can determine the period and pulse width of a signal. to measure period, two successive edges of the same polarity are captured. to measure pulse width, two altern ate polarity edges are captured. in most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to an internal clock (ph2). these asynchrono us capture requests are synchronized to ph2 so that the latching occurs on the opposite half cycle of ph 2 from when the timer counter is being incremented. this synchronization process introduces a delay from wh en the edge occurs to when the counter value is detected. because these delays offset each other when the time between two edges is being measured, the delay can be ignored. when an input capture is being used with an output compare, there is a similar delay between the actual compare point and when the output pin changes state. table 9-1. timer summary xtal frequencies control bits pr1, pr0 4.0 mhz 8.0 mhz 12.0 mhz other rates 1.0 mhz 2.0 mhz 3.0 mhz (e) 1000 ns 500 ns 333 ns (1/e) main timer count rates 0 0 1 count ? overflow ? 1000 ns 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms (e/1) (e/2 16 ) 0 1 1 count ? overflow ? 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 87.381 ms (e/4) (e/2 18 ) 1 0 1 count ? overflow ? 8.0 s 524.29 ms 4.0 s 262.14 ms 2.667 s 174.76 ms (e/8) (e/2 19 ) 1 1 1 count ? overflow ? 16.0 s 1.049 s 8.0 s 524.29 ms 5.333 s 349.52 ms (e/16) (e/2 20 )
timing systems m68hc11e family data sheet, rev. 5.1 130 freescale semiconductor figure 9-2. capture/compare block diagram capture compare block mcu e clk 16-bit latch clk pa0/ic3 4 3 5 6 7 8 2 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a pin control oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tflg 1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f pa1/ic2 pa2/ic1 pa3/oc5/ ic4/oc1 pa4/oc4/ oc1 pa5/oc3/ oc1 pa6/oc2/ oc1 pa7/oc1/ pai i4/o5 16-bit comparator = toc1 (hi) toc1 (lo) 16-bit comparator = toc2 (hi) toc2 (lo) 16-bit comparator = toc3 (hi) toc3 (lo) 16-bit comparator = toc4 (hi) toc4 (lo) 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk 16-bit comparator = ti4/o5 (hi) ti4/o5 (lo) 16-bit free-running counter tcnt (hi) tcnt (lo) 9 toi tof interrupt requests (further qualified by i bit in ccr) taps for rti, cop watchdog, and pulse accumulator prescaler divide by 1, 4, 8, or 16 pr1 pr0 16-bit timer bus oc5 ic4 to pulse accumulator tmsk 1 interrupt enables cforc force output compare pin functions
input capture m68hc11e family data sheet, rev. 5.1 freescale semiconductor 131 the control and status bits that implement the input capture functions are contained in: pulse accumulator control register (pactl) timer control 2 register (tctl2) timer interrupt mask 1 register (tmsk1) timer interrupt flag 2 register (tflg1) to configure port a bit 3 as an input capture, clear t he ddra3 bit of the pactl register. note that this bit is cleared out of reset. to enable pa3 as the fourth input capture, set the i4/o5 bit in the pactl register. otherwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the ddra3 bit is set (configuring pa3 as an output), and ic4 is enabled, then writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/o5 r egister is acting as ic4. 9.3.1 timer control register 2 use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture function. the input capture functions operate inde pendently of each other and can capture the same tcnt value if the input edges are detected within the same timer count cycle. edgxb and edgxa ? input capture edge control bits there are four pairs of these bits. each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit. ic4 functions only if the i4/o5 bit in the pactl register is set. refer to table 9-2 for timer control configuration. 9.3.2 timer input capture registers when an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-b it parallel transfer. timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase 2 clock so that the count value is stable whenever a capture occurs. the timer input c apture registers are not affected by reset. input capture values can be read from a pair of 8-bit read -only registers. a read of the high-order byte of an address: $1021 bit 7654321bit 0 read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset:00000000 figure 9-3. timer control register 2 (tctl2) table 9-2. timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge
timing systems m68hc11e family data sheet, rev. 5.1 132 freescale semiconductor input capture register pair inhibits a new captur e transfer for one bus cycle. if a double-byte read instruction, such as load double accumulator d (ldd), is used to read the captured value, coherency is assured. when a new input capture oc curs immediately after a high-orde r byte read, transfer is delayed for an additional cycle but the value is not lost. register name: timer input capture 1 register (high) address: $1010 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name: timer input capture 1 register (low) address: $1011 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 9-4. timer input capture 1 register pair (tic1) register name: timer input capture 2 register (high) address: $1012 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name: timer input capture 2 register (low) address: $1013 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 9-5. timer input capture 2 register pair (tic2) register name: timer input capture 3 register (high) address: $1014 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name: timer input capture 3 register (low) address: $1015 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 9-6. timer input capture 3 register pair (tic3)
output compare m68hc11e family data sheet, rev. 5.1 freescale semiconductor 133 9.3.3 timer input capture 4 /output compare 5 register use ti4/o5 as either an input capture register or an output compare register, depending on the function chosen for the pa3 pin. to enable it as an input capture pin, set the i4/o5 bit in the pulse accumulator control register (pactl) to logic level 1. to use it as an output compare register, set the i4/o5 bit to a logic level 0. refer to 9.7 pulse accumulator . 9.4 output compare use the output compare (oc) function to program an acti on to occur at a specific time ? when the 16-bit counter reaches a specified value. for each of the five output compare functions, there is a separate 16-bit compare register and a dedicated 16-bit com parator. the value in the compare register is compared to the value of the free-running counter on every bus cycle. when the compare register matches the counter value, an output compare status flag is set. the flag can be used to initiate the automatic actions for that output compare function. to produce a pulse of a specific duration, write a val ue to the output compare register that represents the time the leading edge of the pulse is to occur. the output compare circuit is configured to set the appropriate output either high or low, depending on the polarity of the pulse being produced. after a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. a value representing the width of the pulse is added to the original value, and then written to the output compare register. because the pi n state changes occur at specific values of the free-running counter, the pulse width c an be controlled accurately at the resolution of the free-running counter, independent of software latencies. to generate an output signal of a specific frequency and duty cycle, repeat this pulse-generating procedure. the five 16-bit read/write output compare register s are: toc1, toc2, toc3, and toc4, and the ti4/o5. ti4/o5 functions under software control as either ic4 or oc5. each of the oc registers is set to $ffff on reset. a value written to an oc register is compared to the free-running counter value during each e-clock cycle. if a match is found, the particular output compare flag is set in timer interrupt flag register 1 (tflg1). if that particular interrupt is enabled in the timer interrupt mask register 1 (tmsk1), an interrupt is generated. in addition to an interrupt, a specified action can be initiated at one or more timer output pins. for oc[5:2], the pin action is co ntrolled by pairs of bits (omx a nd olx) in the tctl1 register. the output action is taken on each successful compare, regardless of whether or not the ocxf flag in the tflg1 register was previously cleared. register name: timer input capture 4/output compare 5 (high) address: $101e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1111111 register name: timer input capture 4/output compare 5 (low) address: $101f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1111111 figure 9-7. timer input capture 4/output compare 5 register pair (ti4/o5)
timing systems m68hc11e family data sheet, rev. 5.1 134 freescale semiconductor oc1 is different from the other output compares in that a successful oc1 compare can affect any or all five of the oc pins. the oc1 output action taken when a match is found is controlled by two 8-bit registers with three bits unimplemented: the output compare 1 mask register, oc1m, and the output compare 1 data register, oc1d. oc1m specifies which port a out puts are to be used, and oc1d specifies what data is placed on these port pins. 9.4.1 timer output compare registers all output compare registers are 16-bit read-write. each is initialized to $ffff at reset. if an output compare register is not used for an output compare function, it can be used as a storage location. a write to the high-order byte of an output compare register pa ir inhibits the output compare function for one bus cycle. this inhibition prevents inappropriate s ubsequent comparisons. coheren cy requires a complete 16-bit read or write. however, if coherency is not needed, byte accesses can be used. for output compare functions, write a comparison va lue to output compare registers toc1?toc4 and ti4/o5. when tcnt value matches the comparison value, specified pin actions occur. register name: timer output compare 1 register (high) address: $1016 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1111111 register name: timer output compare 1 register (low) address: $1017 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1111111 figure 9-8. timer output compare 1 register pair (toc1) register name: timer output compare 2 register (high) address: $1018 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1111111 register name: timer output compare 2 register (low) address: $1019 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1111111 figure 9-9. timer output compare 2 register pair (toc2)
output compare m68hc11e family data sheet, rev. 5.1 freescale semiconductor 135 9.4.2 timer compar e force register the cforc register allows forced early compares. fo c[1:5] correspond to the five output compares. these bits are set for each output compare that is to be forced. the action taken as a result of a forced compare is the same as if there were a match between the ocx register and the free-running counter, except that the corresponding interrupt status flag bits are not set. the forced channels trigger their programmed pin actions to occur at the next timer count transition after the write to cforc. the cforc bits should not be used on an output compare function that is programmed to toggle its output on a successful compare because a normal com pare that occurs immediately before or after the force can result in an undesirable operation. register name: timer output compare 3 register (high) address: $101a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1111111 register name: timer output compare 3 register (low) address: $101b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1111111 figure 9-10. timer output compare 3 register pair (toc3) register name: timer output compare 4 register (high) address: $101c bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1111111 register name: timer output compare 4 register (low) address: $101d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1111111 figure 9-11. timer output compare 4 register pair (toc4) address: $100b bit 7654321bit 0 read: foc1 foc2 fo c3 foc4 foc5 write: reset:00000000 = unimplemented figure 9-12. timer compare force register (cforc)
timing systems m68hc11e family data sheet, rev. 5.1 136 freescale semiconductor foc[1:5] ? force output comparison bit when the foc bit associated with an output com pare circuit is set, the output compare circuit immediately performs the action it is progr ammed to do when an output match occurs. 0 = not affected 1 = output x action occurs bits [2:0] ? unimplemented always read 0 9.4.3 output comp are mask register use oc1m with oc1 to specify the bits of port a that are affected by a successful oc1 compare. the bits of the oc1m register correspond to pa[7:3]. oc1m[7:3] ? output compare masks 0 = oc1 disabled 1 = oc1 enabled to control the corresponding pin of port a bits [2:0] ? unimplemented always read 0 9.4.4 output comp are data register use this register with oc1 to specify the data that is to be stored on the affected pin of port a after a successful oc1 compare. when a successful oc1 compare occurs, a data bit in oc1d is stored in the corresponding bit of port a for each bit that is set in oc1m. if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] ? unimplemented always read 0 address: $100c bit 7654321bit 0 read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset:00000000 = unimplemented figure 9-13. output compare 1 mask register (oc1m) address: $100d bit 7654321bit 0 read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset:00000000 = unimplemented figure 9-14. output compare 1 data register (oc1d)
output compare m68hc11e family data sheet, rev. 5.1 freescale semiconductor 137 9.4.5 timer counter register the 16-bit read-only tcnt register contains the pres caled value of the 16-bit timer. a full counter read addresses the most significant byte (msb) first. a read of this address causes the least significant byte (lsb) to be latched into a buffer for the next cpu cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the msb read cycle. 9.4.6 timer control register 1 the bits of this register specify the action taken as a result of a successful ocx compare. om[2:5] ? output mode bits ol[2:5] ? output level bits these control bit pairs are encoded to specify the action taken after a successful ocx compare. oc5 functions only if the i4/o5 bit in t he pactl register is clear. refer to table 9-3 for the coding. register name: timer counter register (high) address: $100e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0000000 register name: timer counter register (low) address: $100f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0000000 = unimplemented figure 9-15. timer counter register (tcnt) address: $1020 bit 7654321bit 0 read: om2ol2om3ol3om4ol4om5ol5 write: reset:00000000 figure 9-16. timer control register 1 (tctl1) table 9-3. timer output compare actions omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1
timing systems m68hc11e family data sheet, rev. 5.1 138 freescale semiconductor 9.4.7 timer interrup t mask 1 register use this 8-bit register to enable or inhibit th e timer input capture and output compare interrupts. oc1i?oc4i ? output compare x interrupt enable bits if the ocxi enable bit is set when the ocxf flag bit is set, a hardware interrupt sequence is requested. i4/o5i ? input capture 4/output compare 5 interrupt enable bit when i4/o5 in pactl is 1, i4/o5i is the input c apture 4 interrupt enable bit. when i4/o5 in pactl is 0, i4/o5i is the output compare 5 interrupt enable bit. ic1i?ic3i ? input capture x interrupt enable bits if the icxi enable bit is set when the icxf flag bi t is set, a hardware interrupt sequence is requested. note bits in tmsk1 correspond bit for bit with flag bits in tflg1. bits in tmsk1 enable the corresponding interrupt sources. 9.4.8 timer interrup t flag 1 register bits in this register indicate when timer system events have occurred. coupled with the bits of tmsk1, the bits of tflg1 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg1 corresponds to a bit in tmsk1 in the same position. clear flags by writing a 1 to the corresponding bit position(s). oc1f?oc4f ? output compare x flag set each time the counter matches output compare x value i4/o5f ? input capture 4/output compare 5 flag set by ic4 or oc5, depending on the function enabled by i4/o5 bit in pactl ic1f?ic3f ? input capture x flag set each time a selected active edge is detected on the icx input line address: $1022 bit 7654321bit 0 read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset:00000000 figure 9-17. timer interrupt mask 1 register (tmsk1) address: $1023 bit 7654321bit 0 read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset:00000000 figure 9-18. timer interrupt flag 1 register (tflg1)
output compare m68hc11e family data sheet, rev. 5.1 freescale semiconductor 139 9.4.9 timer interrup t mask 2 register use this 8-bit register to enable or inhibit timer overflow and real-t ime interrupts. the timer prescaler control bits are included in this register. toi ? timer overflow interrupt enable bit 0 = tof interrupts disabled 1 = interrupt requested when tof is set to 1 rtii ? real-time interrupt enable bit refer to 9.5 real-time interrupt (rti) . paovi ? pulse accumulator overflow interrupt enable bit refer to 9.7.3 pulse accumulator status and interrupt bits . paii ? pulse accumulator input edge interrupt enable bit refer to 9.7.3 pulse accumulator status and interrupt bits . bits [3:2] ? unimplemented always read 0 pr[1:0] ? timer prescaler select bits these bits are used to select the prescaler divide -by ratio. in normal modes, pr[1:0] can be written only once, and the write must be within 64 cycles after reset. refer to table 9-1 and table 9-4 for specific timing values. note bits in tmsk2 correspond bit for bit with flag bits in tflg2. bits in tmsk2 enable the corresponding interrupt sources. address: $1024 bit 7654321bit 0 read: toi rtii paovi paii pr1 pr0 write: reset:00000000 = unimplemented figure 9-19. timer interrupt mask 2 register (tmsk2) table 9-4. timer prescale pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16
timing systems m68hc11e family data sheet, rev. 5.1 140 freescale semiconductor 9.4.10 timer interr upt flag register 2 bits in this register indicate when certain timer system events have occurred. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow t he timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corre sponds to a bit in tmsk2 in the same position. clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif ? real-time (periodic) interrupt flag refer to 9.5 real-time interrupt (rti) . paovf ? pulse accumulator overflow interrupt flag refer to 9.7 pulse accumulator . paif ? pulse accumulator input edge interrupt flag refer to 9.7 pulse accumulator . bits [3:0] ? unimplemented always read 0 9.5 real-time interrupt (rti) the real-time interrupt (rti) feature, used to gener ate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (rtr1 and rtr0) in the pulse accumulator control (pactl) register. the rtii bit in the tmsk2 register enables the interrupt capability. the four different rates available are a product of the mcu oscillator freq uency and the value of bits rtr[1:0]. refer to table 9-5 , which shows the periodic real-time interrupt rates. the clock source for the rti function is a free-running clock that cannot be stopped or interrupted except by reset. this clock causes the time between successive rti timeouts to be a constant that is address: $1025 bit 7654321bit 0 read: tof rtif paovf paif write: reset:00000000 = unimplemented figure 9-20. timer interrupt flag 2 register (tflg2) table 9-5. rti rates rtr[1:0] e = 3 mhz e = 2 mhz e = 1 mhz e = x mhz 0 0 2.731 ms 4.096 ms 8.192 ms (e/2 13 ) 0 1 5.461 ms 8.192 ms 16.384 ms (e/2 14 ) 1 0 10.923 ms 16.384 ms 32.768 ms (e/2 15 ) 1 1 21.845 ms 32.768 ms 65.536 ms (e/2 16 )
real-time interrupt (rti) m68hc11e family data sheet, rev. 5.1 freescale semiconductor 141 independent of the software latencies associated with flag clearing and service. for this reason, an rti period starts from the previous timeout, not from when rtif is cleared. every timeout causes the rtif bit in tflg2 to be set, and if rtii is set, an interrupt request is generated. after reset, one entire rti period elapses before the rtif is set for the first time. refer to the 9.4.9 timer interrupt mask 2 register , 9.5.2 timer interrupt flag register 2 , and 9.5.3 pulse accumulator control register . 9.5.1 timer interrup t mask register 2 this register contains the real-time interrupt enable bits. toi ? timer overflow interrupt enable bit 0 = tof interrupts disabled 1 = interrupt requested when tof is set to 1 rtii ? real-time interrupt enable bit 0 = rtif interrupts disabled 1 = interrupt requested when rtif set to 1 paovi ? pulse accumulator overflow interrupt enable bit refer to 9.7 pulse accumulator . paii ? pulse accumulator input edge bit refer to 9.7 pulse accumulator . bits [3:2] ? unimplemented always read 0 pr[1:0] ? timer prescaler select bits refer to table 9-4 . note bits in tmsk2 correspond bit for bit with flag bits in tflg2. bits in tmsk2 enable the corresponding interrupt sources. address: $1024 bit 7654321bit 0 read: toi rti paovi paii pr1 pr0 write: reset:00000000 = unimplemented figure 9-21. timer interrupt mask 2 register (tmsk2)
timing systems m68hc11e family data sheet, rev. 5.1 142 freescale semiconductor 9.5.2 timer interrup t flag register 2 bits of this register indicate the occurrence of timer system events. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow the timer subsyste m to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif ? real-time interrupt flag the rtif status bit is automatically set to 1 at the end of every rti period. to clear rtif, write a byte to tflg2 with bit 6 set. paovf ? pulse accumulator overflow interrupt flag refer to 9.7 pulse accumulator . paif ? pulse accumulator input edge interrupt flag refer to 9.7 pulse accumulator . bits [3:0] ? unimplemented always read 0 9.5.3 pulse accumulat or control register bits rtr[1:0] of this register select the rate fo r the rti system. the remaining bits control the pulse accumulator and ic4/oc5 functions. ddra7 ? data direction for port a bit 7 refer to chapter 6 parallel input/output (i/o) ports . paen ? pulse accumulator system enable bit refer to 9.7 pulse accumulator . pamod ? pulse accumulator mode bit refer to 9.7 pulse accumulator . address: $1025 bit 7654321bit 0 read: tof rtif paovf paif write: reset:00000000 = unimplemented figure 9-22. timer interrupt flag 2 register (tflg2) address: $1026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 9-23. pulse accumulator control register (pactl)
computer operating properly (cop) watchdog function m68hc11e family data sheet, rev. 5.1 freescale semiconductor 143 pedge ? pulse accumulator edge control bit refer to 9.7 pulse accumulator . ddra3 ? data direction for port a bit 3 refer to chapter 6 parallel input/output (i/o) ports . i4/o5 ? input capture 4/output compare bit refer to 9.7 pulse accumulator . rtr[1:0] ? rti interrupt rate select bits these two bits determine the rate at which the rt i system requests interr upts. the rti system is driven by an e divided by 2 13 rate clock that is compensated so it is independent of the timer prescaler. these two control bits select an additional division factor. refer to table 9-5 . 9.6 computer operating properly (cop) watchdog function the clocking chain for the cop function, tapped off of th e main timer divider chain, is only superficially related to the main timer system. the cr[1:0] bits in the option register and the nocop bit in the config register determine the status of the cop f unction. one additional register, coprst, is used to arm and clear the cop watchdog reset system. refer to chapter 5 resets and interrupts for a more detailed discussion of the cop function. 9.7 pulse accumulator the m68hc11 family of mcus has an 8-bit counter that can be configured to operate either as a simple event counter or for gated time accumulation, depending on the state of the pamod bit in the pactl register. refer to the pulse accumulator block diagram, figure 9-24 . in the event counting mode, the 8-bit counter is clocked to increasing values by an exter nal pin. the maximum clocking rate for the external event counting mode is the e clock divided by two. in gated time accumulation mode, a free-running e-clock divide-by-64 signal drives th e 8-bit counter, but only while the external pai pin is activated. refer to table 9-6 . the pulse accumulator counter can be read or written at any time. pulse accumulator control bits are also located within two timer registers, tmsk2 and tflg2, as described in the following paragraphs. table 9-6. pulse accumulator timing crystal frequency e clock cycle time e 64 pacnt overflow 4.0 mhz 1 mhz 1000 ns 64 s 16.384 ms 8.0 mhz 2 mhz 500 ns 32 s 8.192 ms 12.0 mhz 3 mhz 333 ns 21.33 s 5.461 ms
timing systems m68hc11e family data sheet, rev. 5.1 144 freescale semiconductor figure 9-24. pulse accumulator pedge pamod paen pactl control internal data bus pacnt 8-bit counter pa7/ pai/ oc1 interrupt requests paif paovf tflg2 interrupt status paovi paii paovf paovi paif paii tmsk2 int enables 1 2 overflow enable disable flag setting clock pai edge paen paen 2 : 1 mux output buffer input buffer and edge detector from main timer oc1 data bus mcu pin e 64 clock from main timer from ddra7
pulse accumulator m68hc11e family data sheet, rev. 5.1 freescale semiconductor 145 9.7.1 pulse accumulat or control register four of this register?s bits control an 8-bit pulse accumulator system. another bit enables either the oc5 function or the ic4 function, while two other bits se lect the rate for the real-time interrupt system. ddra7 ? data direction for port a bit 7 refer to chapter 6 parallel input/output (i/o) ports . paen ? pulse accumulator system enable bit 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ? pulse accumulator mode bit 0 = event counter 1 = gated time accumulation pedge ? pulse accumulator edge control bit this bit has different meanings depending on the state of the pamod bit, as shown in table 9-7 . ddra3 ? data direction for port a bit 3 refer to chapter 6 parallel input/output (i/o) ports . i4/o5 ? input capture 4/output compare 5 bit 0 = output compare 5 function enable (no ic4) 1 = input capture 4 function enable (no oc5) rtr[1:0] ? rti interrupt rate select bits refer to 9.5 real-time interrupt (rti) . address: $1026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 9-25. pulse accumulator control register (pactl) table 9-7. pulse accumulator edge control pamod pedge action on clock 0 0 pai falling edge increments the counter. 0 1 pai rising edge increments the counter. 1 0 a 0 on pai inhibits counting. 1 1 a 1 on pai inhibits counting.
timing systems m68hc11e family data sheet, rev. 5.1 146 freescale semiconductor 9.7.2 pulse accumulat or count register this 8-bit read/write register contains the count of external input events at the pai input or the accumulated count. the pacnt is readable even if pai is not active in gated time accumulation mode. the counter is not affected by reset and can be read or written at any time. counting is synchronized to the internal ph2 clock so that incrementing and reading occur during opposite half cycles. 9.7.3 pulse accumulator st atus and interrupt bits the pulse accumulator control bits , paovi and paii, paovf and paif, are located within timer registers tmsk2 and tflg2. paovi and paovf ? pulse accumulator interrupt enable and overflow flag the paovf status bit is set each time the pulse accu mulator count rolls over from $ff to $00. to clear this status bit, write a 1 in the corresponding data bit position (bit 5) of the tflg2 register. the paovi control bit allows configuring the pulse accumulato r overflow for polled or interrupt-driven operation and does not affect the state of paovf. when paovi is 0, pulse accumulator overflow interrupts are inhibited, and the system operates in a polled mo de, which requires that paovf be polled by user software to determine when an overflow has occurre d. when the paovi control bit is set, a hardware interrupt request is generated each time paovf is se t. before leaving the interrupt service routine, software must clear paovf by writing to the tflg2 register. address: $1027 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 9-26. pulse accumula tor count register (pacnt) address: $1024 bit 7654321bit 0 read: toi rtii paovi paii pr1 pr0 write: reset:00000000 = unimplemented figure 9-27. timer interrupt mask 2 register (tmsk2) address: $1025 bit 7654321bit 0 read: tof rtif paovf paif write: reset:00000000 = unimplemented figure 9-28. timer interrupt flag 2 register (tflg2)
pulse accumulator m68hc11e family data sheet, rev. 5.1 freescale semiconductor 147 paii and paif ? pulse accumulator input edge interrupt enable bit and flag the paif status bit is automatically set each time a selected edge is detected at the pa7/pai/oc1 pin. to clear this status bit, write to the tflg2 register with a 1 in the corresponding data bit position (bit 4). the paii control bit allows configuring the pul se accumulator input edge detect for polled or interrupt-driven operation but does not affect setti ng or clearing the paif bit. when paii is 0, pulse accumulator input interrupts are inhibited, and the sy stem operates in a polled mode. in this mode, the paif bit must be polled by user software to de termine when an edge has occurred. when the paii control bit is set, a hardware interrupt request is generated each time paif is set. before leaving the interrupt service routine, software must cl ear paif by writing to the tflg2 register.
timing systems m68hc11e family data sheet, rev. 5.1 148 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 149 chapter 10 electrical characteristics 10.1 introduction this section contains electrical specific ations for the m68hc11 e-series devices. 10.2 maximum ratings for standa rd and extended voltage devices maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 10.5 dc electrical characteristics , 10.6 supply currents and power dissipation , 10.7 mc68l11e9/e20 dc electrical characteristics , and 10.8 mc68l11e9/e20 supply currents and power dissipation for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating symbol value unit supply voltage v dd ?0.3 to +7.0 v input voltage v in ?0.3 to +7.0 v current drain per pin (1) excluding v dd , v ss , av dd , v rh , v rl , and xirq/ v ppe 1. one pin at a time, observing maximum power dissipation limits i d 25 ma storage temperature t stg ?55 to +150 c
electrical characteristics m68hc11e family data sheet, rev. 5.1 150 freescale semiconductor 10.3 functional operating range 10.4 thermal characteristics rating symbol value unit operating temperature range mc68hc(7)11ex mc68hc(7)11exc mc68hc(7)11exv mc68hc(7)11exm mc68hc811e2 mc68hc811e2c mc68hc811e2v mc68hc811e2m mc68l11ex t a t l to t h 0 to +70 ?40 to +85 ?40 to +105 ?40 to +125 0 to +70 ?40 to +85 ?40 to +105 ?40 to +125 ?20 to +70 c operating voltage range v dd 5.0 10% v characteristic symbol value unit average junction temperature t j t a + (p d ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 48-pin plastic dip (mc68hc811e2 only) 56-pin plastic sdip 52-pin plastic leaded chip carrier 52-pin plastic thin quad flat pack (tqfp) 64-pin quad flat pack ja 50 50 50 85 85 c/w total power dissipation (1) 1. this is an approximate value, neglecting p i/o . p d p int + p i/o k / t j + 273 c w device internal power dissipation p int i dd v dd w i/o pin power dissipation (2) 2. for most applications, p i/o p int and can be neglected. p i/o user-determined w a constant (3) 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . k p d (t a + 273 c) + ja p d 2 w/ c
dc electrical characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 151 10.5 dc electrical characteristics characteristics (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit output voltage (2) i load = 10.0 a all outputs except xtal all outputs except xtal, reset , and moda 2. v oh specification for reset and moda is not applicable bec ause they are open-drain pins. v oh specification not appli- cable to ports c and d in wired-or mode. v ol , v oh ? v dd ?0.1 0.1 ? v output high voltage (2) i load = ?0.8 ma, v dd = 4.5 v all outputs except xtal, reset , and moda v oh v dd ?0.8 ?v output low voltage i load = 1.6 ma all outputs except xtal v ol ?0.4 v input high voltage all inputs except reset reset v ih 0.7 v dd 0.8 v dd v dd + 0.3 v dd + 0.3 v input low voltage, all inputs v il v ss ?0.3 0.2 v dd v i/o ports, 3-state leakage v in = v ih or v il pa7, pa3, pc[7:0], pd[5:0], as/stra, moda/lir , reset i oz ? 10 a input leakage current (3) v in = v dd or v ss pa[2:0], irq , xirq modb/v stby (xirq on eprom-based devices) 3. refer to 10.13 analog-to-digital converter characteristics and 10.14 mc68l11e9/e20 analog-to- digital converter char- acteristics for leakage current for port e. i in ? ? 1 10 a ram standby voltage, power down v sb 4.0 v dd v ram standby current, power down i sb ?10 a input capacitance pa[2:0], pe[7:0], irq , xirq , extal pa7, pa3, pc[7:0], pd[5:0], as/stra, moda/lir , reset c in ? ? 8 12 pf output load capacitance all outputs except pd[4:1] pd[4:1] c l ? ? 90 100 pf
electrical characteristics m68hc11e family data sheet, rev. 5.1 152 freescale semiconductor 10.6 supply currents and power dissipation characteristics (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit run maximum total supply current (2) single-chip mode2 mhz 3 mhz expanded multiplexed mode2 mhz 3 mhz 2. extal is driven with a square wave, and t cyc = 500 ns for 2 mhz rating t cyc = 333 ns for 3 mhz rating v il 0.2 v v ih v dd ? 0.2 v no dc loads i dd ? ? ? ? 15 27 27 35 ma wait maximum total supply current (2) (all peripheral functions shut down) single-chip mode2 mhz 3 mhz expanded multiplexed mode2 mhz 3 mhz w idd ? ? ? ? 6 15 10 20 ma stop maximum total supply current (2) single-chip mode, no clocks?40 c to +85 c > +85 c to +105 c > +105 c to +125 c s idd ? ? ? 25 50 100 a maximum power dissipation single-chip mode2 mhz 3 mhz expanded multiplexed mode2 mhz 3 mhz p d ? ? ? ? 85 150 150 195 mw
mc68l11e9/e20 dc electri cal characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 153 10.7 mc68l11e9/e20 dc el ectrical characteristics characteristics (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit output voltage (2) i load = 10.0 a all outputs except xtal all outputs except xtal, reset , and moda 2. v oh specification for reset and moda is not applicable bec ause they are open-drain pins. v oh specification not appli- cable to ports c and d in wired-or mode. v ol , v oh ? v dd ?0.1 0.1 ? v output high voltage (2) i load = ?0.5 ma, v dd = 3.0 v i load = ?0.8 ma, v dd = 4.5 v all outputs except xtal, reset , and moda v oh v dd ?0.8 ?v output low voltage i load = 1.6 ma, v dd = 5.0 v i load = 1.0 ma, v dd = 3.0 v all outputs except xtal v ol ?0.4 v input high voltage all inputs except reset reset v ih 0.7 v dd 0.8 v dd v dd + 0.3 v dd + 0.3 v input low voltage, all inputs v il v ss ?0.3 0.2 v dd v i/o ports, 3-state leakage v in = v ih or v il pa7, pa3, pc[7:0], pd[5:0], as/stra, moda/lir , reset i oz ? 10 a input leakage current (3) v in = v dd or v ss pa[2:0], irq , xirq modb/v stby (xirq on eprom-based devices) 3. refer to 10.13 analog-to-digital converter characteristics and 10.14 mc68l11e9/e20 analog-to- digital converter char- acteristics for leakage current for port e. i in ? ? 1 10 a ram standby voltage, power down v sb 2.0 v dd v ram standby current, power down i sb ?10 a input capacitance pa[2:0], pe[7:0], irq , xirq , extal pa7, pa3, pc[7:0], pd[5:0], as/stra, moda/lir , reset l? ? 8 12 pf output load capacitance all outputs except pd[4:1] pd[4:1] c l ? ? 90 100 pf
electrical characteristics m68hc11e family data sheet, rev. 5.1 154 freescale semiconductor 10.8 mc68l11e9/e20 supply currents and power dissipation characteristic (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol 1 mhz 2 mhz unit run maximum total supply current (2) single-chip mode v dd = 5.5 v v dd = 3.0 v expanded multiplexed mode v dd = 5.5 v v dd = 5.5 v 2. extal is driven with a square wave, and t cyc = 500 ns for 2 mhz rating t cyc = 333 ns for 3 mhz rating v il 0.2 v v ih v dd ? 0.2 v no dc loads i dd 8 4 14 7 15 8 27 14 ma wait maximum total supply current (2) (all peripheral functions shut down) single-chip mode v dd = 5.5 v v dd = 3.0 v expanded multiplexed mode v dd = 5.5 v v dd = 3.0 v w idd 3 1.5 5 2.5 6 3 10 5 ma stop maximum total supply current (2) single-chip mode, no clocks v dd = 5.5 v v dd = 3.0 v s idd 50 25 50 25 a maximum power dissipation single-chip mode 2 mhz 3 mhz expanded multiplexed mode 2 mhz 3 mhz p d 44 12 77 21 85 24 150 42 mw
mc68l11e9/e20 supply curr ents and power dissipation m68hc11e family data sheet, rev. 5.1 freescale semiconductor 155 figure 10-1. test methods notes : 1. full test loads are applied during all dc electrical tests and ac timing measurements. 2. during ac timing measurements, inputs are driven to 0.4 volts and v dd ? 0.8 volts while timing clocks, strobes inputs v dd ? 0.8 volts 0.4 volts v dd ~ nominal timing nom 20% of v dd 70% of v dd v dd ? 0.8 volts 0.4 volts v ss ~ v dd ~ nom outputs 0.4 volts dc testing clocks, strobes inputs 20% of v dd 70% of v dd v ss ~ v dd ~ spec timing v dd ? 0.8 volts 20% of v dd 70% of v dd 0.4 volts v ss ~ v dd ~ spec outputs ac testing (note 2) 20% of v dd 70% of v dd 20% of v dd v ss ~ spec measurements are taken at 20% and 70% of v dd points.
electrical characteristics m68hc11e family data sheet, rev. 5.1 156 freescale semiconductor 10.9 control timing characteristic (1) (2) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless oth- erwise noted 2. reset is recognized during the first clock cycle it is held low. internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. refer to chapter 5 resets and interrupts for further detail. symbol 1.0 mhz 2.0 mhz 3.0 mhz unit minmaxminmaxminmax frequency of operation f o dc 1.0 dc 2.0 dc 3.0 mhz e-clock period t cyc 100 0 ? 500 ? 333 ? ns crystal frequency f xtal ?4.0?8.0?12.0mhz external oscillator frequency 4 f o dc 4.0 dc 8.0 dc 12.0 mhz processor contro l setup time t pcsu = 1/4 t cyc + 50 ns t pcsu 300 ? 175 ? 133 ? ns reset input pulse width to guarantee external reset vector minimum input time (can be pre-empted by internal reset) pw rstl 8 1 ? ? 8 1 ? ? 8 1 ? ? t cyc mode programming setup time t mps 2?2?2? t cyc mode programming hold time t mph 10 ? 10 ? 10 ? ns interrupt pulse width, irq edge-sensitive mode pw irq = t cyc + 20 ns pw irq 102 0 ? 520 ? 353 ? ns wait recovery startup time t wrs ?4?4?4 t cyc timer pulse width input capture pulse accumulator input pw tim = t cyc + 20 ns pw tim 102 0 ? 520 ? 353 ? ns
mc68l11e9/e20 control timing m68hc11e family data sheet, rev. 5.1 freescale semiconductor 157 10.10 mc68l11e9/e20 control timing figure 10-2. timer inputs characteristic (1) (2) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted 2. reset is recognized during the first clock cycle it is held low. internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. refer to chapter 5 resets and interrupts for further detail. symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation f o dc 1.0 dc 2.0 mhz e-clock period t cyc 1000 ? 500 ? ns crystal frequency f xtal ?4.0?8.0mhz external oscillator frequency 4 f o dc 4.0 dc 8.0 mhz processor contro l setup time t pcsu = 1/4 t cyc + 75 ns t pcsu 325 ? 200 ? ns reset input pulse width to guarantee external reset vector minimum input time (can be pre-empted by internal reset) pw rstl 8 1 ? ? 8 1 ? ? t cyc mode programming setup time t mps 2?2? t cyc mode programming hold time t mph 10 ? 10 ? ns interrupt pulse width, irq edge-sensitive mode pw irq = t cyc + 20 ns pw irq 1020 ? 520 ? ns wait recovery startup time t wrs ?4?4 t cyc timer pulse width input capture pulse accumulator input pw tim = t cyc + 20 ns pw tim 1020 ? 520 ? ns notes : 1. rising edge sensitive input 2. falling edge sensitive input 3. maximum pulse accumulator clocking rate is e-clock frequency divided by 2. pa7 (2) (3) pa7 (1) (3) pa[2:0] (2) pa[2:0] (1) pw tim
m68hc11e family data sheet, rev. 5.1 158 freescale semiconductor electrical characteristics figure 10-3. por external reset timing diagram t pcsu address moda, modb e extal v dd reset 4064 t cyc fffe fffe fffe new pc fffe ffff fffe fffe fffe new pc fffe ffff fffe t mph pw rstl t mps
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 159 mc68l11e9/e20 control timing figure 10-4. stop recovery timing diagram pw irq t stopdelay 3 irq 1 irq or xirq e sp ? 8 sp ? 8 fff2 (fff4) new pc stop addr stop addr + 1 address 4 stop addr stop addr + 1 stop addr + 1 stop addr + 1 stop addr + 2 sp?sp?7 fff3 (fff5) opcode resume program with instruction which follows the stop instruction. notes : 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0). internal address 5 clocks 3. t stopdelay = 4064 t cyc if dly bit = 1 or 4 t cyc if dly = 0.
m68hc11e family data sheet, rev. 5.1 160 freescale semiconductor electrical characteristics figure 10-5. wait recovery from interrupt timing diagram t pcsu pcl pch, yl, yh, xl, xh, a, b, ccr stack registers e r/w address wait addr wait addr + 1 irq , xirq , or internal interrupts note: reset also causes recovery from wait. sp sp ? 1 sp ? 2?sp ? 8 sp ? 8 sp ? 8?sp ? 8 sp ? 8 sp ? 8 sp ? 8 vector addr vector addr + 1 new pc t wrs
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 161 mc68l11e9/e20 control timing figure 10-6. interrupt timing diagram e pw irq sp ? 8 sp ? 8 address new pc next opcode next op + 1 irq 1 vector addr sp ? 7 t pcsu irq 2 , xirq , or internal interrupt sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 sp ? 5 sp ? 6 vector addr + 1 op code ? ? notes : 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) data pcl pch iyl iyh ixl ixh b a ccr ? ? vect msb vect lsb op code r/w
electrical characteristics m68hc11e family data sheet, rev. 5.1 162 freescale semiconductor 10.11 peripheral port timing characteristic (1) (2) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted 2. ports c and d timing is valid for active drive. (cwom and dwom bits are not set in pioc and spcr registers, respec- tively.) symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation e-clock frequency f o dc 1.0 dc 2.0 dc 3.0 mhz e-clock period t cyc 1000 ? 500 ? 333 ? ns peripheral data setup time mcu read of ports a, c, d, and e t pdsu 100 ? 100 ? 100 ? ns peripheral data hold time mcu read of ports a, c, d, and e t pdh 50 ? 50 ? 50 ? ns delay time, peripheral data write t pwd = 1/4 t cyc + 100 ns mcu writes to port a mcu writes to ports b, c, and d t pwd ? ? 200 350 ? ? 200 225 ? ? 200 183 ns port c input data setup time t is 60 ? 60 ? 60 ? ns port c input data hold time t ih 100 ? 100 ? 100 ? ns delay time, e fall to strb t deb = 1/4 t cyc + 100 ns t deb ? 350 ? 225 ? 183 ns setup time, stra asserted to e fall (3) 3. if this setup time is met, strb acknowledges in the next cycle. if it is not met, the response may be delayed one more cycle . t aes 0?0?0?ns delay time, stra asserted to port c data output valid t pcd ? 100 ? 100 ? 100 ns hold time, stra negated to port c data t pch 10 ? 10 ? 10 ? ns 3-state hold time t pcz ? 150 ? 150 ? 150 ns
mc68l11e9/e20 peripheral port timing m68hc11e family data sheet, rev. 5.1 freescale semiconductor 163 10.12 mc68l11e9/e20 peripheral port timing figure 10-7. port read timing diagram characteristic (1) (2) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted 2. ports c and d timing is valid for active drive. (cwom and dwom bits are not set in pioc and spcr registers, respec- tively.) symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation e-clock frequency f o dc 1.0 dc 2.0 mhz e-clock period t cyc 1000 ? 500 ? ns peripheral data setup time mcu read of ports a, c, d, and e t pdsu 100 ? 100 ? ns peripheral data hold time mcu read of ports a, c, d, and e t pdh 50 ? 50 ? ns delay time, peripheral data write t pwd = 1/4 t cyc + 150 ns mcu writes to port a mcu writes to ports b, c, and d t pwd ? ? 250 400 ? ? 250 275 ns port c input data setup time t is 60 ? 60 ? ns port c input data hold time t ih 100 ? 100 ? ns delay time, e fall to strb t deb = 1/4 t cyc + 150 ns t deb ? 400 ? 275 ns setup time, stra asserted to e fall (3) 3. if this setup time is met, strb acknowledges in the next cycle. if it is not met, the response may be delayed one more cycle . t aes 0?0?ns delay time, stra asserted to port c data output valid t pcd ? 100 ? 100 ns hold time, stra negated to port c data t pch 10 ? 10 ? ns 3-state hold time t pcz ? 150 ? 150 ns
electrical characteristics m68hc11e family data sheet, rev. 5.1 164 freescale semiconductor figure 10-8. port write timing diagram figure 10-9. simple input strobe timing diagram figure 10-10. simple output strobe timing diagram figure 10-11. port c input handshake timing diagram t pwd e mcu write to port b previous port data new data vali d strb (out) port b t deb mcu write to port b t pwd t deb new data valid previous port data e port b strb (out) port c input hndshk tim e port c (in) t deb strb (out) read portcl 1 stra (in) t deb "ready" notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). t aes t is t ih e strb (0ut) stra (in) port c (in) notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). ?ready? read portcl (1) t deb t aes t is t ih t deb
mc68l11e9/e20 peripheral port timing m68hc11e family data sheet, rev. 5.1 freescale semiconductor 165 figure 10-12. port c output handshake timing diagram figure 10-13. 3-state variation of output handshake timing diagram (stra enables output buffer) port c output hndshk tim t pwd e previous port data new data vali d strb (out) port c (out) write portcl 1 "ready" stra (in) notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). t deb t deb t aes e port c (out) strb (in) stra (in) notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). ?ready? write portcl (1) t deb t aes t pwd t deb previous port data new data valid e t deb port c (out) (ddr = 1) read portcl 1 strb (out) t pwd "ready" notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). t aes old data new data vali d port c (out) (ddr = 0) stra (in) a) stra active before portcl write new data vali d port c (out) (ddr = 0) stra (in) b) stra active after portcl write t deb t pcz t pch t pcz t pch t pcd t pcd e port c (out) ddr = 1 strb (out) stra (in) port c (out) ddr = 0 stra (in) port c (out) ddr = 0 a) stra active before portcl write b) stra active after portcl write read portcl (1) t pwd t deb t deb ?ready? t aes t pcd t pcd t pch t pcz t pch t pcz old data new data valid new data valid notes: 1. after reading pioc with staf set 2. figure shows rising edge stra (ega = 1) and high true strb (invb = 1). t pch
electrical characteristics m68hc11e family data sheet, rev. 5.1 166 freescale semiconductor 10.13 analog-to-digital converter characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h, 750 khz e 3.0 mhz, unless otherwise noted parameter (2) 2. source impedances greater than 10 k ? affect accuracy adversely because of input leakage. min absolute 2.0 mhz 3.0 mhz uni t max max resolution number of bits resolved by a/d converter ? 8 ? ? bits non-linearity maximum deviation from the ideal a/d transfer characteristics ?? 1/2 1 ls b zero error difference between the output of an ideal and an actual for 0 input voltage ?? 1/2 1 ls b full scale error difference between the output of an ideal and an actual a/d for full-scale input voltage ?? 1/2 1 ls b total unadjusted error maximum sum of non-linearity, zero error, and full-scale error ?? 1/2 1/2 ls b quantization error uncertainty because of converter resolution ? ? 1/2 1/2 ls b absolute accuracy difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included ?? 1 2 ls b conversion range analog input voltage range v rl ? v rh v rh v v rh maximum analog reference voltage (3) 3. performance verified down to 2.5 v ? v r , but accuracy is tested and guaranteed at ? v r = 5 v 10%. v rl ? v dd +0.1 v dd +0.1 v v rl minimum analog reference voltage (2) v ss ?0.1 ? v rh v rh v ? v r minimum difference between v rh and v rl (2) 3???v conversion time total time to perform a single a/d conversion: e clock internal rc oscillator ? ? 32 ? ? t cyc +32 ? t cyc +32 t cy c s monotonicity conversion result never decreases with an increase in input voltage; has no missing codes ? guaranteed ? ? ? zero input reading conversion result when v in = v rl 00 ? ? ? hex full scale reading conversion result when v in = v rh ? ? ff ff hex sample acquisition time analog input acquisition sampling time: e clock internal rc oscillator ? ? 12 ? ? 12 ? 12 t cy c s sample/hold capacitance input capacitance during sample pe[7:0] ? 20 typical ? ? pf input leakage input leakage on a/d pins pe[7:0] v rl , v rh ? ? ? ? 400 1.0 400 1.0 na a
mc68l11e9/e20 analog-to-digital converter characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 167 10.14 mc68l11e9/e20 analog-to- digital converter characteristics characteristic (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h, 750 khz e 2.0 mhz, unless otherwise noted parameter (2) 2. source impedances greater than 10 k ? affect accuracy adversely because of input leakage. min absolute max unit resolution number of bits resolved by a/d converter ? 8 ? bits non-linearity maximum deviation from the ideal a/d transfer characteristics ?? 1lsb zero error difference between the output of an ideal and an actual for 0 input voltage ?? 1lsb full scale error difference between the output of an ideal and an actual a/d for full-scale input voltage ?? 1lsb total unadjusted error maximum sum of non-linearity, zero error, and full-scale error ?? 1/2 lsb quantization error uncertainty because of converter resolution ? ? 1/2 lsb absolute accuracy difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all e rror sources included ?? 2lsb conversion range analog input voltage range v rl ? v rh v v rh maximum analog reference voltage v rl ? v dd + 0.1 v v rl minimum analog reference voltage v ss ?0.1 ? v rh v ? v r minimum difference between v rh and v rl 3.0 ? ? v conversion time total time to perform a single analog-to-digital conversion: e clock internal rc oscillator ? ? 32 ? ? t cyc + 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes ? guaranteed ? ? zero input reading conversion result when v in = v rl 00 ? ? hex full scale reading conversion result when v in = v rh ??ffhex sample acquisition time analog input acquisition sampling time: e clock internal rc oscillator ? ? 12 ? ? 12 t cyc s sample/hold capacitance input capacitance during sample pe[7:0] ? 20 typical ? pf input leakage input leakage on a/d pins pe[7:0] v rl , v rh ? ? ? ? 400 1.0 na a
electrical characteristics m68hc11e family data sheet, rev. 5.1 168 freescale semiconductor 10.15 expansion bus timing characteristics num characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless oth- erwise noted symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 dc 3.0 mhz 1 cycle time t cyc 1000 ? 500 ? 333 ? ns 2 pulse width, e low (2) , pw el = 1/2 t cyc ?23 ns 2. formula only for dc to 2 mhz pw el 477 ? 227 ? 146 ? ns 3 pulse width, e high (2) , pw eh = 1/2 t cyc ?28 ns pw eh 472 ? 222 ? 141 ? ns 4a e and as rise time t r ?20?20?20ns 4b e and as fall time t f ?20?20?15ns 9 address hold time (2) (3)a , t ah = 1/8 t cyc ?29.5 ns 3. input clocks with duty cycles ot her than 50% affect bus performance. timing pa rameters affect ed by input clock duty cycle are identified by (a) and (b). to recalculate the approximate bu s timing values, substitute the following expressions in place of 1/8 t cyc in the above formulas, where applicable: (a) (1?dc) 1/4 t cyc (b) dc 1/4 t cyc where: dc is the decimal value of du ty cycle percentage (high time) t ah 95.5 ? 33 ? 26 ? ns 12 non-multiplexed address valid time to e rise t av = pw el ?(t asd + 80 ns) (2) (3)a t av 281.5 ? 94 ? 54 ? ns 17 read data setup time t dsr 30 ? 30 ? 30 ? ns 18 read data hold time, max = t mad t dhr 0 145.5 0 83 0 51 ns 19 write data delay time, t ddw = 1/8 t cyc + 65.5 ns (2) (3)a t ddw ? 190.5 ? 128 71 ns 21 write data hold time, t dhw = 1/8 t cyc ?29.5 ns (2) (3)a t dhw 95.5 ? 33 ? 26 ? ns 22 multiplexed address valid time to e rise t avm = pw el ?(t asd + 90 ns) (2) (3)a t avm 271.5 ? 84 ? 54 ? ns 24 multiplexed address valid time to as fall t asl = pw ash ?70 ns (2) t asl 151 ? 26 ? 13 ? ns 25 multiplexed address hold time t ahl = 1/8 t cyc ?29.5 ns (2) (3)b t ahl 95.5 ? 33 ? 31 ? ns 26 delay time, e to as rise, t asd = 1/8 t cyc ?9.5 ns (2) (3)a t asd 115.5 ? 53 ? 31 ? ns 27 pulse width, as high, pw ash = 1/4 t cyc ?29 ns (2) pw ash 221 ? 96 ? 63 ? ns 28 delay time, as to e rise, t ased = 1/8 t cyc ?9.5 ns (2) (3)b t ased 115.5 ? 53 ? 31 ? ns 29 mpu address access time (3)a t acca = t cyc ?(pw el ?t avm ) ?t dsr ?t f t acca 744.5 ? 307 ? 196 ? ns 35 mpu access time, t acce = pw eh ?t dsr t acce ? 442 ? 192 111 ns 36 multiplexed address delay (previous cycle mpu read) t mad = t asd + 30 ns (2) (3)a t mad 145.5 ? 83 ? 51 ? ns
mc68l11e9/e20 expansion bus timing characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 169 10.16 mc68l11e9/e20 expansio n bus timing characteristics num characteristic (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 mhz 1cycle time t cyc 1000 ? 500 ? ns 2 pulse width, e low, pw el = 1/2 t cyc ?25 ns pw el 475 ? 225 ? ns 3 pulse width, e high, pw eh = 1/2 t cyc ?30 ns pw eh 470 ? 220 ? ns 4a e and as rise time t r ? 25 ? 25 ns 4b e and as fall time t f ? 25 ? 25 ns 9 address hold time (2) (2)a , t ah = 1/8 t cyc ?30 ns 2. input clocks with duty cycles ot her than 50% affect bus performance. timing pa rameters affect ed by input clock duty cycle are identified by (a) and (b). to recalculate the approximate bu s timing values, substitute the following expressions in place of 1/8 t cyc in the above formulas, where applicable: (a) (1?dc) 1/4 t cyc (b) dc 1/4 t cyc where: dc is the decimal value of du ty cycle percentage (high time). t ah 95 ? 33 ? ns 12 non-multiplexed address valid time to e rise t av = pw el ?(t asd + 80 ns) (2)a t av 275 ? 88 ? ns 17 read data setup time t dsr 30 ? 30 ? ns 18 read data hold time , max = t mad t dhr 01500 88ns 19 write data delay time, t ddw = 1/8 t cyc + 70 ns (2)a t ddw ? 195 ? 133 ns 21 write data hold time, t dhw = 1/8 t cyc ?30 ns (2)a t dhw 95 ? 33 ? ns 22 multiplexed address valid time to e rise t avm = pw el ?(t asd + 90 ns) (2)a t avm 268 ? 78 ? ns 24 multiplexed address valid time to as fall t asl = pw ash ?70 ns t asl 150 ? 25 ? ns 25 multiplexed address hold time, t ahl = 1/8 t cyc ?30 ns (2)b t ahl 95 ? 33 ? ns 26 delay time, e to as rise, t asd = 1/8 t cyc ?5 ns (2)a t asd 120 ? 58 ? ns 27 pulse width, as high, pw ash = 1/4 t cyc ?30 ns pw ash 220 ? 95 ? ns 28 delay time, as to e rise, t ased = 1/8 t cyc ?5 ns (2)b t ased 120 ? 58 ? ns 29 mpu address access time (3)a t acca = t cyc ?(pw el ?t avm ) ?t dsr ?t f t acca 735 ? 298 ? ns 35 mpu access time, t acce = pw eh ?t dsr t acce ? 440 ? 190 ns 36 multiplexed address delay (previous cycle mpu read) t mad = t asd + 30 ns (2)a t mad 150 ? 88 ? ns
electrical characteristics m68hc11e family data sheet, rev. 5.1 170 freescale semiconductor figure 10-14. multiplexed expansion bus timing diagram e as 1 4a 9 address/data (multiplexed) read write 12 2 3 4b 4a 4b 29 35 17 18 19 21 25 24 27 36 22 26 28 address address data data r/w, address (non-mux) note: measurement points sh own are 20% and 70% of v dd . mux bus ti m 1 2 3 4b 4a 12 36 22 35 17 29 18 9 21 19 4a 25 24 4b 26 27 28 e r/w , address non-multiplexed address/data multiplexed as read write address data address data note: measurement points shown are 20% and 70% of v dd .
serial peripheral interface timing characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 171 10.17 serial peripheral inte rface timing characteristics num characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless other- wise noted symbol e9 e20 unit min max min max frequency of operation e clock f o dc 3.0 dc 3.0 mhz e-clock period t cyc 333 ? 333 ? ns operating frequency master slave f op(m) f op(s) f o /32 dc f o /2 f o f o /128 dc f o /2 f o mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 32 ? 2 1 128 ? t cyc 2 enable lead time (2) slave 2. time to data active from high-impedance state t lead(s) 1?1? t cyc 3 enable lag time (2) slave t lag(s) 1?1? t cyc 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s t cyc ?25 1/2 t cyc ?25 16 t cyc ? t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s t cyc ?25 1/2 t cyc ?25 16 t cyc ? t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? 30 30 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? 30 30 ? ? ns 8 slave access time cpha = 0 cpha = 1 t a 0 0 40 40 0 0 40 40 ns 9 disable time (hold time to high-impedance state) slave t dis ?50?50ns 10 data valid (3) (after enable edge) 3. assumes 200 pf load on sck, mosi, and miso pins t v ?50?50ns 11 data hold time (outputs) (after enable edge) t ho 0?0?ns
electrical characteristics m68hc11e family data sheet, rev. 5.1 172 freescale semiconductor 10.18 mc68l11e9/e20 serial peir pheral interface characteristics num characteristic (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted symbol e9 e20 unit min max min max frequency of operation e clock f o dc 2.0 dc 2.0 mhz e-clock period t cyc 500 ? 500 ? ns operating frequency master slave f op(m) f op(s) f o /32 dc f o /2 f o f o /128 dc f o /2 f o mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 32 ? 2 1 128 ? t cyc 2 enable lead time (2) slave 2. time to data active from high-impedance state t lead(s) 1?1? t cyc 3 enable lag time (2) slave t lag(s) 1?1? t cyc 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s t cyc ?30 1/2 t cyc ?30 16 t cyc ? t cyc ?30 1/2 t cyc ?30 64 t cyc ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s t cyc ?30 1/2 t cyc ?30 16 t cyc ? t cyc ?30 1/2 t cyc ?30 64 t cyc ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? 40 40 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? 40 40 ? ? ns 8 slave access time cpha = 0 cpha = 1 t a 0 0 50 50 0 0 50 50 ns 9 disable time (hold time to high-impedance state) slave t dis ?60?60ns 10 data valid (3) (after enable edge) 3. assumes 100 pf load on sck, mosi, and miso pins t v ?60?60ns 11 data hold time (outputs) (after enable edge) t ho 0?0?ns
mc68l11e9/e20 serial peirpheral interface characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 173 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) figure 10-15. spi timing diagram (sheet 1 of 2) sck input sck output miso input mosi output ss input 1 11 6 7 msb in bit 6 . . . 1 lsb in master msb out master lsb out bit 6 . . . 1 11 (ref) 5 4 cpol = 0 cpol = 1 ss is held high on master. see note see note note: this first clock edge is generated inte rnally but is not seen at the sck pin. 5 4 10 sck input sck output miso input mosi output ss input 1 11 msb in bit 6 . . . 1 lsb in master msb out master lsb out bit 6 . . . 1 11 (ref) 5 4 cpol = 0 cpol = 1 ss is held high on master. see note see note note: this first clock edge is generated inte rnally but is not seen at the sck pin. 5 4 10 10 (ref) 6 7
electrical characteristics m68hc11e family data sheet, rev. 5.1 174 freescale semiconductor a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) figure 11-15. spi timing diagram (sheet 2 of 2) sck input sck input mosi input miso output ss input 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 2 8 cpol = 0 cpol = 1 3 note: not defined but normally msb of character just received slave 11 see note 9 5 5 10 11 sck input sck input mosi input miso output ss input 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 2 8 cpol = 0 cpol = 1 3 note: not defined but normally lsb of character previ ously transmitted slave 11 see note 9 5 5 10 10 4
eeprom characteristics m68hc11e family data sheet, rev. 5.1 freescale semiconductor 175 10.19 eeprom characteristics 10.20 mc68l11e9/e20 eeprom characteristics 10.21 eprom characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h temperature range unit ?40 to 85 c ?40 to 105 c ?40 to 125 c programming time (2) < 1.0 mhz, rco enabled 1.0 to 2.0 mhz, rco disabled 2.0 mhz (or anytime rco enabled) 10 20 10 15 must use rco 15 20 must use rco 20 ms erase time (2) byte, row, and bulk 2. the rc oscillator (rco) must be enabled (by setting the csel bit in the option register) for eeprom programming and erasure when the e-clock frequency is below 1.0 mhz. 10 10 10 ms write/erase endurance 10,000 10,000 10,000 cycles data retention 10 10 10 years characteristic (1) 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h temperature range ?20 to 70 c unit programming time (2) 3 v, e 2.0 mhz, rco enabled 5 v, e 2.0 mhz, rco enabled 2. the rc oscillator (rco) must be enabled (by setting the csel bit in the option register) for eeprom programming and erasure. 25 10 ms erase time (2) (byte, row, and bulk) 3 v, e 2.0 mhz, rco enabled 5 v, e 2.0 mhz, rco enabled 25 10 ms write/erase endurance 10,000 cycles data retention 10 years characteristics (1) 1. v dd = 5.0 vdc 10% symbol min typ max unit programming voltage (2) 2. during eprom programming of the mc68hc711e9 device, the v ppe pin circuitry may latch-up and be damaged if the input current is not limited to 10 ma. for more information please refer to mc68hc711e9 8-bit microcontroller unit mask set errata 3 (freescale document order number 68hc711e9mse3. v ppe 11.75 12.25 12.75 v programming current (3) 3. typically, a 1-k ? series resistor is sufficient to limit th e programming current for the mc68hc711e9. a 100- ? series resis- tor is sufficient to limit the programming current for the mc68hc711e20. i ppe ?310ma programming time t eprog 224ms
electrical characteristics m68hc11e family data sheet, rev. 5.1 176 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 177 chapter 11 ordering information and mechanical specifications 11.1 introduction this section provides ordering information for the e-series devices grouped by: standard devices custom rom devices extended voltage devices in addition, mechanical spec ifications for the foll owing packaging options: 52-pin plastic-leaded chip carrier (plcc) 52-pin windowed ceramic-leaded chip carrier (clcc) 64-pin quad flat pack (qfp) 52-pin thin quad flat pack (tqfp) 56-pin shrink dual in-line package with .070-inch lead spacing (sdip) 48-pin plastic dip (.100-inch lead spacing), mc68hc811e2 only 11.2 standard device ordering information description config temperature frequency mc order number 52-pin plastic leaded chip carrier (plcc) buffalo rom $0f ?40 c to +85 c 2 mhz mc68hc11e9bcfn2 3 mhz mc68hc11e9bcfn3 no rom $0d ?40 c to +85 c 2 mhz mc68hc11e1cfn2 3 mhz mc68hc11e1cfn3 ?40 c to +105 c 2 mhz mc68hc11e1vfn2 ?40 c to +125 c 2 mhz mc68hc11e1mfn2 no rom, no eeprom $0c ?40 c to +85 c 2 mhz mc68hc11e0cfn2 3 mhz mc68hc11e0cfn3 ?40 c to +105 c 2 mhz mc68hc11e0vfn2 ?40 c to +125 c 2 mhz mc68hc11e0mfn2
ordering information and mechanical specifications m68hc11e family data sheet, rev. 5.1 178 freescale semiconductor 52-pin plastic leaded chip carrier (plcc) (continued) otprom $0f ?40 c to +85 c 2 mhz mc68hc711e9cfn2 3 mhz mc68hc711e9cfn3 ?40 c to +105 c 2 mhz mc68hc711e9vfn2 ?40 c to +125 c 2 mhz mc68hc711e9mfn2 otprom, enhanced security feature $0f ?40 c to +85 c 2 mhz mc68s711e9cfn2 20 kbytes otprom $0f 0 c to +70 c 3 mhz mc68hc711e20fn3 ?40 c to +85 c 2 mhz mc68hc711e20cfn2 3 mhz mc68hc711e20cfn3 ?40 c to +105 c 2 mhz mc68hc711e20vfn2 ?40 c to +125 c 2 mhz mc68hc711e20mfn2 no rom, 2 kbytes eeprom $ff 0 c to +70 c 2 mhz mc68hc811e2fn2 ?40 c to +85 c 2 mhz mc68hc811e2cfn2 ?40 c to +105 c 2 mhz mc68hc811e2vfn2 ?40 c to +125 c 2 mhz mc68hc811e2mfn2 64-pin quad flat pack (qfp) buffalo rom $0f ?40 c to +85 c 2 mhz mc68hc11e9bcfu2 3 mhz mc68hc11e9bcfu3 no rom $0d ?40 c to +85 c 2 mhz mc68hc11e1cfu2 3 mhz mc68hc11e1cfu3 ?40 c to +105 c 2 mhz mc68hc11e1vfu2 no rom, no eeprom $0c ?40 c to +85 c 2 mhz mc68hc11e0cfu2 ?40 c to +105 c 2 mhz mc68hc11e0vfu2 20 kbytes otprom $0f 0 c to +70 c 3 mhz mc68hc711e20fu3 ?40 c to +85 c 2 mhz mc68hc711e20cfu2 3 mhz mc68hc711e20cfu3 ?40 c to +105 c 2 mhz mc68hc711e20vfu2 ?40 c to +125 c 2 mhz mc68hc711e20mfu2 52-pin thin quad flat pack (tqfp) buffalo rom $0f ?40 c to +85 c 2 mhz mc68hc11e9bcpb2 3 mhz mc68hc11e9bcpb3 description config temperature frequency mc order number
custom rom device or dering information m68hc11e family data sheet, rev. 5.1 freescale semiconductor 179 11.3 custom rom device ordering information 52-pin windowed ceramic l eaded chip carrier (clcc) eprom $0f ?40 c to +85 c 2 mhz mc68hc711e9cfs2 3 mhz mc68hc711e9cfs3 ?40 c to +105 c 2 mhz mc68hc711e9vfs2 ?40 c to +125 c 2 mhz mc68hc711e9vfs2 20 kbytes eprom $0f 0 c o +70 c 3 mhz mc68hc711e20fs3 ?40 c to +85 c 2 mhz mc68hc711e20cfs2 3 mhz mc68hc711e20cfs3 ?40 c to +105 c 2 mhz mc68hc711e20vfs2 ?40 c to +125 c 2 mhz mc68hc711e20mfs2 48-pin dual in-line package (dip) ? mc68hc811e2 only no rom, 2 kbytes eeprom $ff 0 c to +70 c 2 mhz mc68hc811e2p2 ?40 c to +85 c 2 mhz mc68hc811e2cp2 ?40 c to +105 c 2 mhz mc68hc811e2vp2 ?40 c to +125 c 2 mhz mc68hc811e2mp2 56-pin dual in-line p ackage with 0.70-inch lead spacing (sdip) buffalo rom $0f ?40 c to +85 c 2 mhz mc68hc11e9bcb2 3 mhz mc68hc11e9bcb3 no rom $0d ?40 c to +85 c 2 mhz mc68hc11e1cb2 3 mhz mc68hc11e1cb3 ?40 c to +105 c 2 mhz mc68hc11e1vb2 ?40 c to +125 c 2 mhz mc68hc11e1mb2 no rom, no eeprom $0c ?40 c to +85 c 2 mhz mc68hc11e0cb2 3 mhz mc68hc11e0cb3 ?40 c to +105 c 2 mhz MC68HC11E0VB2 ?40 c to +125 c 2 mhz mc68hc11e0mb2 description temperature frequency mc order number 52-pin plastic leaded chip carrier (plcc) custom rom 0 c to +70 c 3 mhz mc68hc11e9fn3 ?40 c to +85 c 2 mhz mc68hc11e9cfn2 3 mhz mc68hc11e9cfn3 ?40 c to +105 c 2 mhz mc68hc11e9vfn2 ?40 c to +125 c 2 mhz mc68hc11e9mfn2 description config temperature frequency mc order number
ordering information and mechanical specifications m68hc11e family data sheet, rev. 5.1 180 freescale semiconductor 20 kbytes custom rom 0 c to +70 c 3 mhz mc68hc11e20fn3 ?40 c to +85 c 2 mhz mc68hc11e20cfn2 3 mhz mc68hc11e20cfn3 ?40 c to +105 c 2 mhz mc68hc11e20vfn2 ?40 c to +125 c 2 mhz mc68hc11e20mfn2 64-pin quad flat pack (qfp) custom rom 0 c to +70 c 3 mhz mc68hc11e9fu3 ?40 c to +85 c 2 mhz mc68hc11e9cfu2 3 mhz mc68hc11e9cfu3 ?40 c to +105 c 2 mhz mc68hc11e9vfu2 ?40 c to +125 c 2 mhz mc68hc11e9mfu2 64-pin quad flat pack (continued) 20 kbytes custom rom 0 c to +70 c 3 mhz mc68hc11e20fu3 ?40 c to +85 c 2 mhz mc68hc11e20cfu2 3 mhz mc68hc11e20cfu3 ?40 c to +105 c 2 mhz mc68hc11e20vfu2 ?40 c to +125 c 2 mhz mc68hc11e20mfu2 52-pin thin quad flat pack (10 mm x 10 mm) custom rom 0 c to +70 c 3 mhz mc68hc11e9pb3 ?40 c to +85 c 2 mhz mc68hc11e9cpb2 3 mhz mc68hc11e9cpb3 ?40 c to +105 c 2 mhz mc68hc11e9vpb2 ?40 c to +125 c 2 mhz mc68hc11e9mpb2 56-pin dual in-line package with 0.70-inch lead spacing (sdip) custom rom 0 c to +70 c 3 mhz mc68hc11e9b3 ?40 c to +85 c 2 mhz mc68hc11e9cb2 3 mhz mc68hc11e9cb3 ?40 c to +105 c 2 mhz mc68hc11e9vb2 ?40 c to +125 c 2 mhz mc68hc11e9mb2 description temperature frequency mc order number
extended voltage device ordering information (3.0 vdc to 5.5 vdc) m68hc11e family data sheet, rev. 5.1 freescale semiconductor 181 11.4 extended voltage device orderi ng information (3.0 vdc to 5.5 vdc) description temperature frequency mc order number 52-pin plastic leaded chip carrier (plcc) custom rom ?20 c to +70 c 2 mhz mc68l11e9fn2 mc68l11e20fn2 no rom 2 mhz mc68l11e1fn2 no rom, no eeprom 2 mhz mc68l11e0fn2 64-pin quad flat pack (qfp) custom rom ?20 c to +70 c 2 mhz mc68l11e9fu2 mc68l11e20fu2 no rom 2 mhz mc68l11e1fu2 no rom, no eeprom 2 mhz mc68l11e0fu2 52-pin thin quad flat pack (10 mm x 10 mm) custom rom ?20 c to +70 c 2 mhz mc68l11e9pb2 no rom 2 mhz mc68l11e1pb2 no rom, no eeprom 2 mhz mc68l11e0pb2 56-pin dual in-line p ackage with 0.70-inch lead spacing (sdip) custom rom ?20 c to +70 c 2 mhz mc68l11e9b2 no rom 2 mhz mc68l11e1b2 no rom, no eeprom 2 mhz mc68l11e0b2
ordering information and mechanical specifications m68hc11e family data sheet, rev. 5.1 182 freescale semiconductor 11.5 52-pin plastic-leade d chip carrier (case 778) ?l? y brk w d d v 52 1 notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t?, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). b u z g1 x view d?d h k1 k f view s m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n 0.004 (0.100) ?t? seating plane m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n a r g g1 c z j e view s ?m? ?n? dim min max min max millimeters inches a 0.785 0.795 19.94 20.19 b 0.785 0.795 19.94 20.19 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 ??? 0.51 ??? k 0.025 ??? 0.64 ??? r 0.750 0.756 19.05 19.20 u 0.750 0.756 19.05 19.20 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y ??? 0.020 ??? 0.50 z 2 10 2 10 g1 0.710 0.730 18.04 18.54 k1 0.040 ??? 1.02 ??? m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n s 0.010 (0.25) l?m s t s n s 0.010 (0.25) l?m s t s n
52-pin windowed ce ramic-leaded chip carrier (case 778b) m68hc11e family data sheet, rev. 5.1 freescale semiconductor 183 11.6 52-pin windowed ceramic-l eaded chip carrier (case 778b) 0.15 (0.006) -t- seating plane m 0.51 (0.020) a s t s b g c k h -b- notes: 1. dimensioni ng and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension r and n do not include glass protrusion. glass protrusion to be 0.25 (0.010) maximum. 4. all dimensions and tolerances include lead trim offset and lead dim min max min max millimeters inches a 0.785 0.795 19.94 20.19 b 0.785 0.795 19.94 20.19 c 0.165 0.200 4.20 5.08 d 0.017 0.021 0.44 0.53 f 0.026 0.032 0.67 0.81 g 0.050 bsc 1.27 bsc h 0.090 0.130 2.29 3.30 j 0.006 0.010 0.16 0.25 k 0.035 0.045 0.89 1.14 n 0.735 0.756 18.67 19.20 r 0.735 0.756 18.67 19.20 s 0.690 0.730 17.53 18.54 n r -a- m 0.51 (0.020) a s t s b s f j m 0.18 (0.007) a s t s b d 52 pl
ordering information and mechanical specifications m68hc11e family data sheet, rev. 5.1 184 freescale semiconductor 11.7 64-pin quad flat pack (case 840c) ???? ? ?? ? ???? g h e c detail a l a 48 s l ?d? ?a? ?b? 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c b v 0.05 (0.002) d s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c seating plane datum plane ?c? ?h? 49 33 32 64 17 1 16 detail c 0.10 (0.004) s a?b m 0.20 (0.008) d s c section b?b f n d base j metal detail a p bb ?a?, ?b?, ?d? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a?b and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.53 (0.021). dambar cannot be located on the lower radius or the foot. 8. dimension k is to be measured from the theoretical intersection of lead foot and leg centerlines. dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.07 2.46 0.081 0.097 d 0.30 0.45 0.012 0.018 e 2.00 0.079 f 0.30 0.012 g 0.80 bsc 0.031 bsc ??? h 0.067 0.250 0.003 0.010 j 0.130 0.230 0.005 0.090 k 0.50 0.66 0.020 0.026 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.130 0.170 0.005 0.007 p 0.40 bsc 0.016 bsc q 2 8 2 8 r 0.13 0.30 0.005 0.012 s 16.20 16.60 0.638 0.654 t 0.20 ref 0.008 ref u 0 ??? 0 ??? v 16.20 16.60 0.638 0.654 x 1.10 1.30 0.043 0.051 2.40 0.094 ??? detail c seating plane m u t r q k x m
52-pin thin quad flat pack (case 848d) m68hc11e family data sheet, rev. 5.1 freescale semiconductor 185 11.8 52-pin thin quad flat pack (case 848d) f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?l?, ?m? and ?n? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). ???? ???? view aa view aa 2 x r r1 ab ab view y section ab?ab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c ??? 1.70 ??? 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l ?x? x=l, m, n 1 13 14 26 27 39 40 52 4x tips 4x n 0.20 (0.008) h l?m n 0.20 (0.008) t l?m 3x view y seating plane c 0.10 (0.004) t 4x 3 4x 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s l?m m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 ?l? ?n? ?m? ?h? ?t? 1 g 1 3 2 07 12 513 07 0 0 ??? ??? ref 12 ref 13 5
ordering information and mechanical specifications m68hc11e family data sheet, rev. 5.1 186 freescale semiconductor 11.9 56-pin dual in-l ine package (case 859) 11.10 48-pin plastic dip (case 767) note the mc68hc811e2 is the only member of the e series that is offered in a 48-pin plastic dual in-line package. ?a? ?b? ?t? 56 29 128 seating plane j 56 pl d 56 pl s a m 0.25 (0.010) t n f g e s b m 0.25 (0.010) t k c h l m dim min max min max millimeters inches a 2.035 2.065 51.69 52.45 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 e 0.035 bsc 0.89 bsc f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010) -a- -b- 48 25 124 -t- seating plane f g detail x 32 pl d 48 pl j s b m 0.25 (0.010) t s a m 0.51 (0.020) t n c k 48 pl m detail x l tip taper notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010). dim min max min max millimeters inches a 2.415 2.445 61.34 62.10 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.55 f 0.040 0.060 1.02 1.52 g 0.100 bsc 2.54 bsc h 0.070 bsc 1.79 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.150 2.92 3.81 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 187 appendix a development support a.1 introduction this section provides information on the develop ment support offered for the e-series devices. a.2 m68hc11 e-series development tools a.3 evs ? evaluation system the evs is an economical tool for designing, debugging, and evaluating target systems based on the m68hc11. evs features include: ? monitor/debugger firmware one-line assembler/disassembler host computer download capability dual memory maps: ? 64-kbyte monitor map that incl udes 16 kbytes of monitor eprom ? m68hc11 e-series user map that in cludes 64 kbytes of emulation ram mcu extension input/output (i/o) port for sing le-chip, expanded, and special-test operation modes rs-232c terminal and host i/o ports logic analyzer connector device package emulation module (1) (2) 1. each mmds11 system consists of a system console (m68mmds 11), an emulation modu le, a flex ca ble, and a target head. 2. a complete evs consists of a platform board (m68hc11pfb ), an emulation module, a flex cable, and a target head. flex cable (1) (2) mmds11 target head (1) (2) spgmr programming adapter (3) 3. each spgmr system consists of a universal serial pr ogrammer (m68spgmr11) and a programming adapter. it can be used alone or in conjunction with the mmds11. mc68hc11e9 mc68hc711e9 52 fn m68em11e20 m68cbl11c m68tc11e20fn52 m68pa11e20fn52 52 pb m68em11e20 m68cbl11c m68tc11e20pb52 m68pa11e20pb52 56 b m68em11e20 m68cbl11b m68tc11e20b56 m68pa11e20b56 64 fu m68em11e20 m68cbl11c m68tc11e20fu64 m68pa11e20fu64 mc68hc11e20 mc68hc711e20 52 fn m68em11e20 m68cbl11c m68tc11e20fn52 m68pa11e20fn52 64 fu m68em11e20 m68cbl11c m68tc11e20fu64 m68pa11e20fu64 mc68hc811e2 48 p m68em11e20 m68cbl11b m68tb11e20p48 m68pa11a8p48 52 fn m68em11e20 m68cbl11c m68tc11e20fn52 m68pa11e20fn52
development support m68hc11e family data sheet, rev. 5.1 188 freescale semiconductor a.4 modular developme nt system (mmds11) the m68mmds11 modular development system (mmd s11) is an emulator system for developing embedded systems based on an m68hc1 1 microcontroller unit (mcu). the mmds11 provides a bus state analyzer (bsa) and real-t ime memory windows. the unit's integrated development environment includes an editor, an assembler, user interface, a nd source-level debug. thes e features significantly reduce the time necessary to develop and debug an embedded mcu system. the unit's compact size requires a minimum of desk space. the mmds11 is one component of freescale's modul ar approach to mcu-based product development. this modular approach allows easy configuration of the mmds11 to fit a wide range of requirements. it also reduces development system cost by allowi ng the user to purchase only the modular components necessary to support the particular mcu derivative. mmds11 features include: real-time, non-intrusive, in-circuit emulation at the mcu?s operating frequency real-time bus state analyzer ? 8 k x 64 real-time trace buffer ? display of real-time trace data as raw data, disassembled instructions, raw data and disassembled instructions, or assembly-language source code ? four hardware triggers for commencing trace and to provide breakpoints ? nine triggering modes ? as many as 8190 pre- or post-trigger points for trace data ? 16 general-purpose logic clips, four of which can be used to trigger the bus state analyzer sequencer ? 16-bit time tag or an optional 24-bit time tag t hat reduces the logic clips traced from 16 to eight four data breakpoints (hardware breakpoints) hardware instruction breakpoints over either the 64-kbyte m68hc11 memory map or over a 1-mbyte bank switched memory map 32 real-time variables, nine of which can be disp layed in the variables window. these variables may be read or written while the mcu is running 32 bytes of real-time memory can be displayed in the memory window. this memory may be read or written while the mcu is running 64 kbytes of fast emulation memory (sram) current-limited target input/output connections six software-selectable oscillator clock source s: five internally generated frequencies and an external frequency via a bus analyzer logic clip command and response logging to ms-dos ? disk files to save session history script command for automatic execution of a sequence of mmds11 commands assembly or c-language source-level debugging with global variable viewing host/emulator communications speeds as high as 57,600 baud for quick program loading ? ms-dos is a registered trademark of microsoft corporation.
spgmr11 ? serial prog rammer for m68hc11 mcus m68hc11e family data sheet, rev. 5.1 freescale semiconductor 189 extensive on-line mcu information via the chipinfo command. view memory map, vectors, register, and pinout information pertaining to the device being emulated host software supports: ? an editor ? an assembler and user interface ? source-level debug ? bus state analysis ?ibm ? mouse a.5 spgmr11 ? serial pr ogrammer for m68hc11 mcus the spgmr11 is a modular eprom/eeprom progr amming tool for all m68hc11 devices. the programmer features interchangeable adapters that allow programming of various m68hc11 package types. programmer features include: programs m68hc11 family devices that contain an eprom or eeprom array. can be operated as a stand-alone programmer connected to a host computer or connected between a host computer and the m68hc11 m odular development system (mmds11) station module uses plug-in programming adapters to accommo date a variety of mcu devices and packages on-board programming voltage circuit eliminates the need for an external 12-volt supply. includes programming software and a user?s manual includes a +5-volt power cable and a db9 to db25 connector adapter ? ibm is a registered trademark145 of international business machines corporation.
development support m68hc11e family data sheet, rev. 5.1 190 freescale semiconductor
m68hc11e family data sheet, rev. 5.1 freescale semiconductor 191 appendix b evbu schematic refer to figure b-1 for a schematic diagram of the m68hc 11evbu universal evaluation board. this diagram is included for reference only.
m68hc11e family data sheet, rev. 5.1 192 freescale semiconductor evbu schematic figure b-1. evbu schematic diagram rxd 4 14 mcu 34 34 mcu 33 33 mcu 32 32 mcu 31 31 mcu 30 30 mcu 29 29 mcu 28 28 mcu 27 27 mcu 20 20 mcu 21 21 mcu 22 22 mcu 23 23 mcu 24 24 mcu 25 25 mcu 43 43 mcu 45 45 mcu 47 47 mcu 49 49 mcu 44 44 mcu 46 46 mcu 48 48 mcu 50 50 mcu 52 52 mcu 51 51 1 v dd 25 pa0/ic3 pa1/ic2 pa2/ic1 pa3/oc5 pa4/oc4 pa5/oc3 pa6/oc2 pa7/oc1 pd0/rxd pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 v rh v rl v ss c7 1 f c8 0.1 f v cc mcu43 (pe0) r4 47 k 2 j2 v cc 1 3 mcu52 (v rh ) r3 1 k c9 0.1 f v cc gnd note 1 1 u2 v cc 2 3 input reset gnd mc34064p v cc mcu17 (reset ) rn1a 47 k 1 2 sw1 notes: 1. default cut traces installed from factory on bottom of the board. 2. x1 is shipped as a ceramic resonator with built-in c apacitors. holes are provided fo r a crystal and two capacitors. master reset mcu21 (pd1/txd) mcu20 (pd0/rxd) 1 2 j9 j8 2 1 note 1 note 1 v cc rn1e 47 k 1 6 pb0/a8 pb1/a9 pb2/a10 pb3/a11 pb4/a12 pb5/a13 pb6/a14 pb7/a15 pc0/ad0 pc1/ad1 pc2/ad2 pc3/ad3 pc4/ad4 pc5/ad5 pc6/ad6 pc7/ad7 e strb/r/w stra/as reset irq xirq moda/lir modb/v stby extal xtal r2 10 m x1 8 mhz c6 27 pf c5 27 pf note 2 5mcu5 6mcu6 4mcu4 17 mcu17 19 mcu19 18 mcu18 3mcu3 2mcu2 42 mcu42 41 mcu41 40 mcu40 39 mcu39 38 mcu38 37 mcu37 36 mcu36 35 mcu35 9mcu9 10 mcu10 11 mcu11 12 mcu12 13 mcu13 14 mcu14 15 mcu15 16 mcu16 7 8 mc68hc11e9fn u3 mcu18 (xirq ) mcu31 (pa3/oc5) mcu19 (irq ) mcu3 (moda/lir ) mcu2 (modb/v stby ) mcu8 mcu7 j6 2 1 j5 2 1 2 1 v cc 1 5 j7 rn1d 47 k v cc 1 4 rn1c 47 k v cc 1 3 rn1b 47 k v cc r1 47 k note 1 2 1 j3 j4 2 1 user?s terminal or pc mcu [2 . . . 52] 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 1 nc v cc v cc c1+ c1? c2+ c2? di1 di2 di3 dd1 dd2 dd3 v cc mc145407 c11 0.1 f 20 18 1 3 15 16 13 14 11 12 19 v dd v ss tx1 rx1 tx2 rx2 tx3 rx3 gnd 17 6 5 8 7 10 9 2 u4 v cc c14 10 f 20 v 2 1 j15 note 1 dcd dtr dsr cts txd p2 connector db25 + + + + c10 c12 c13
? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor application note an1060 rev. 1.1, 07/2005 m68hc11 bootstrap mode by jim sibigtroth mike rhoades john langan austin, texas introduction the m68hc11 family of mcus (microcontroller unit s) has a bootstrap mode that allows a user-defined program to be loaded into the internal random-access memory (ram) by way of the serial communications interface (sci); the m68hc11 then executes this loaded program. the loaded program can do anything a normal user program can do as well as anything a factory test program can do because protected control bits are accessible in bootstrap mode. although the bootstrap mode is a single-chip mode of operation, expanded mode resources are acce ssible because the mode control bits can be changed while operating in the bootstrap mode. this application note explains the operation and a pplication of the m68hc11 bootstrap mode. although basic concepts associated with this mode are quite simp le, the more subtle implications of these functions require careful consideration. useful applications of this mode are overlooked due to an incomplete understanding of bootstrap mode. also, common problems associated with bootstrap mode could be avoided by a more complete understanding of its operation and implications. topics discussed in this application note include: basic operation of the m68hc11 bootstrap mode general discussion of bootstrap mode uses detailed explanation of on-chip bootstrap logic detailed explanation of bootstrap firmware bootstrap firmware vs. eeprom security incorporating the bootstrap mode into a system driving bootstrap mode from another m68hc11 driving bootstrap mode from a personal computer common bootstrap mode problems variations for specific versions of m68hc11 commented listings for selected m68hc11 bootstrap roms
m68hc11 bootstrap mode, rev. 1.1 194 freescale semiconductor basic bootstrap mode basic bootstrap mode this section describes only basic functions of the bootstrap mode. other functions of the bootstrap mode are described in detail in the rema inder of this application note. when an m68hc11 is reset in bootstrap mode, the reset vector is fetched from a small internal read-only memory (rom) called the bootstrap rom or boot rom. the firmware program in this boot rom then controls the bootloading process, in this manner: first, the on-chip sci (serial communications interf ace) is initialized. the first character received ($ff) determines which of two possible baud rates should be used for the remaining characters in the download operation. next, a binary program is received by t he sci system and is stored in ram. finally, a jump instruction is executed to pass cont rol from the bootloader firmware to the user?s loaded program. bootstrap mode is useful both at the component level and after the mcu has been embedded into a finished user system. at the component level, freescale uses bootstrap mode to control a monitored burn-in program for the on-chip electrically erasable progr ammable read-only memory (eeprom ). units to be tested are loaded into special circuit boards that each hold many mcus. these boards are then placed in burn-in ovens. driver boards outside the ovens download an eeprom exerci se and diagnostic program to all mcus in parallel. the mcus under test in dependently exercise t heir internal eeprom and monitor programming and erase operations. this technique could be utilized by an end user to load program information into the eprom or eeprom of an m68hc11 before it is instal led into an end product. as in the burn-in setup, many m68hc11s can be gang programmed in parallel. th is technique can also be used to program the eprom of finished products after final assembly. freescale also uses bootstrap mode for program ming target devices on the m68hc11 evaluation modules (evm). because bootstrap mode is a pr ivileged mode like specia l test, the eeprom-based configuration register (config) can be pr ogrammed using bootstrap mode on the evm. the greatest benefits from bootstrap mode are realiz ed by designing the finished system so that bootstrap mode can be used after final assembly. the finished sy stem need not be a single-chip mode application for the bootstrap mode to be useful because the expansion bus can be enabled after resetting the mcu in bootstrap mode. allowing this capability requires almost no hardware or design cost and the addition of this capability is invisible in the end product until it is needed. the ability to control the embedded processor thr ough downloaded programs is achieved without the disassembly and chip-swapping usual ly associated with such control. this mode provides an easy way to load non-volatile memories such as eeprom with calibration tables or to program the application firmware into a one-time programmabl e (otp) mcu after final assembly. another powerful use of bootstrap mode in a finished assembly is for final te st. short programs can be downloaded to check parts of the system, includi ng components and circuitry external to the embedded mcu. if any problems appear during product devel opment, diagnostic programs can be downloaded to find the problems, and corrected routines can be downl oaded and checked before incorporating them into the main application program.
bootstrap mode logic m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 195 bootstrap mode can also be used to interactively cali brate critical analog sensors. since this calibration is done in the final assembled system , it can compensate for any errors in discrete interface circuitry and cabling between the sensor and the analog inputs to the mcu. note that this calibration routine is a downloaded program that does not take up space in the normal application program. bootstrap mode logic in the m68hc11 mcus, very little logic is dedicated to the bootstrap mode. consequently, this mode adds almost no extra cost to the mcu system. the biggest piece of circuitry for bootstrap mode is the small boot rom. this rom is 192 bytes in the original mc68hc11a8, but some of the newest members of the m68hc11 family, such as the mc68hc711k4, hav e as much as 448 bytes to accommodate added features. normally, this boot rom is present in the me mory map only when the mcu is reset in bootstrap mode to prevent interference with the user?s normal memory space. the enable for this rom is controlled by the read boot rom (rboot) control bit in the highes t priority interrupt (hprio) register. the rboot bit can be written by software whenever the mcu is in special test or special bootstrap modes; when the mcu is in normal modes, rboot reverts to 0 and bec omes a read-only bit. all other logic in the mcu would be present whether or not there was a bootstrap mode. figure 1 shows the composite memory map of the mc68hc 711e9 in its four basic modes of operation, including bootstrap mode. the active mode is det ermined by the mode a (mda) and special mode (smod) control bits in the hprio control register. thes e control bits are in turn controlled by the state of the mode a (moda) and mode b (modb) pins during reset. table 1 shows the relationship between the state of these pins during reset, the selected mode, and the state of the mda, smod, and rboot control bits. refer to the composite memory map and information in table 1 for the following discussion. the mda control bit is determined by the state of the moda pin as the mcu leaves reset. mda selects between single-chip and expanded operating modes. whe n mda is 0, a single-chip mode is selected, either normal single-chip mode or special bootstrap mode. when mda is 1, an expanded mode is selected, either normal expanded mode or special test mode. the smod control bit is determined by the inverted state of the modb pin as the mcu leaves reset. smod controls whether a normal mode or a specia l mode is selected. when smod is 0, one of the two normal modes is selected, either normal single-c hip mode or normal expanded mode. when smod is 1, one of the two special modes is selected, either spec ial bootstrap mode or special test mode. when either special mode is in effect (smod = 1), certain privileges are in effect, for instance, the ability to write to the mode control bits and fetching the reset and inte rrupt vectors from $bfxx rather than $ffxx. table 1. mode selection summary input pins mode selected control bits in hprio modb moda rboot smod mda 1 0 normal single chip 0 0 0 0 0 normal expanded 0 0 1 0 0 special bootstrap 1 1 0 0 1 special test 0 1 1
m68hc11 bootstrap mode, rev. 1.1 196 freescale semiconductor boot rom firmware the alternate vector locations are achieved by simply driving address bit a14 lo w during all vector fetches if smod = 1. for special test mode, the alternate ve ctor locations assure that the reset vector can be fetched from external memory space so the test sy stem can control mcu operation. in special bootstrap mode, the small boot rom is enabled in the memory map by rboot = 1 so the reset vector will be fetched from this rom and the bootloader firmware will control mcu operation. rboot is reset to 1 in bootstrap mode to enable the small boot rom. in the other three modes, rboot is reset to 0 to keep the boot rom out of the memory map. while in special test mode, smod = 1, which allows the rboot control bit to be written to 1 by software to enable the boot rom for testing purposes. boot rom firmware the main program in the boot rom is the bootloader, which is automatically executed as a result of resetting the mcu in bootstrap mode. some newer versi ons of the m68hc11 family have additional utility programs that can be called from a downloaded program . one utility is available to program eprom or otp versions of the m68hc11. a second utility allo ws the contents of memory locations to be uploaded to a host computer. in the mc68hc711k4 boot rom, a section of code is used by freescale for stress testing the on-chip eeprom. these test and utility pr ograms are similar to self-test rom programs in other mcus except that the boot rom does not use valuable space in the normal memory map. bootstrap firmware is also involv ed in an optional eeprom security fu nction on some versions of the m68hc11. this eeprom security feature prevents a soft ware pirate from seeing what is in the on-chip eeprom. the secured state is invo ked by programming the no securi ty (nosec) eeprom bit in the config register. once this nosec bit is programm ed to 0, the mcu will ignore the mode a pin and always come out of reset in normal single-chip m ode or special bootstrap mode, depending on the state of the mode b pin. normal single-chip mode is th e usual way a secured part would be used. special bootstrap mode is used to disengage the security function (only a fter the contents of eeprom and ram have been erased). refer to the m68hc11 reference manual , freescale document order number m68hc11rm/ad, for additional information on the secu rity mode and complete list ings of the boot roms that support the eeprom security functions. automatic selection of baud rate the bootloader program in the mc68hc711e9 ac commodates either of two baud rates. the higher of these baud rates (7812 baud at a 2-mhz e-clock rate) is used in systems that operate from a binary frequency crystal such as 2 23 hz (8.389 mhz). at this crystal frequency, the baud rate is 8192 baud, which was used extens ively in automotive applications. the second baud rate available to the m68hc 11 bootloader is 1200 baud at a 2-mhz e-clock rate. some of the newest versions of the m68 hc11, including the mc68hc11f1 and mc68hc117k4, accommodate other baud rates using the same differentiation technique explained here. refer to the reference numbers in square brackets in figure 2 during the following explanation. note software can change some aspects of the memory map after reset.
automatic selection of baud rate m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 197 figure 2 shows how the bootloader program differentiates between the default baud rate (7812 baud at a 2-mhz e-clock rate) and the alternate baud rate (1200 baud at a 2-mhz e-clock rate). the host computer sends an initial $ff character, which is used by the bootloader to determine the baud rate that will be used for the downloading operation. the top half of figure 2 shows normal reception of $ff. receive data samples at [1] detect the falling edge of the start bit and then verify the start bit by taking a sample at the center of the start bit time. samples are then taken at the middle of each bit time [2] to reconstruct the value of the received character (all 1s in this case). a sample is then taken at the middle of the stop bit time as a framing check (a 1 is expec ted) [3]. unless another character immediately follows this $ff character, the receive data line will idle in the high state as shown at [4]. the bottom half of figure 2 shows how the receiver will incorrectly receive the $ff character that is sent from the host at 1200 baud. because the receiver is set to 7812 baud, the receive data samples are taken at the same times as in the upper half of figure 2 . the start bit at 1200 baud [5] is 6.5 times as long as the start bit at 7812 baud [6]. figure 1. mc68hc711e9 composite memory map $0000 512-byte ram $01ff $1000 $103f $b600 $b7ff $bf00 $bfff $ffff $bfc0 $ffc0 single chip expanded multiplexed external external special bootstrap special test external external external 64-byte register block 512-byte eeprom boot rom 12k user eprom (or otp) (may be remapped to any 4k boundary) (may be remapped to any 4k boundary) (may be disabled by an eeprom bit) (may be disabled by an eeprom bit) special mode vectors normal mode vectors $bfc0 $bfff $ffc0 $ffff moda = 0 modb = 1 moda = 1 modb = 1 moda = 0 modb = 0 moda = 1 modb = 0 external note: software can chan g e some as p ects of the memor y ma p after reset. $d000
m68hc11 bootstrap mode, rev. 1.1 198 freescale semiconductor main bootloader program figure 2. automatic de tection of baud rate samples taken at [7] detect the failing edge of the start bit and verify it is a logic 0. samples taken at the middle of what the receiver interprets as the first five bit times [8] detect logic 0s. the sample taken at the middle of what the receiver interprets as bit 5 [9] may detect either a 0 or a 1 because the receive data has a rising transition at about this time. the samples for bits 6 and 7 detect 1s, causing the receiver to think the received character was $c0 or $e0 [10] at 7812 baud instead of the $ff which was sent at 1200 baud. the stop bit sample detects a 1 as expected [11], but this detection is actually in the middle of bit 0 of the 1200 baud $ff character. the sci receiver is not confused by the rest of the 1200 baud $ff character because the receive data line is high [12] just as it would be for the idle condition. if a character other than $ff is sent as the first character, an sci receive error could result. main bootloader program figure 3 is a flowchart of the main bootloader progr am in the mc68hc711e9. this bootloader demonstrates the most important features of the bootloaders used on all m68hc11 family members. for complete listings of other m68hc11 versions, refer to listing 3. mc68hc711e9 bootloader rom at the end of this application note, and to appendix b of the m68hc11 reference manual , freescale document order number m68hc11rm/ad. the reset vector in the boot rom points to the star t [1] of this program. the initialization block [2] establishes starting conditions and sets up the sci and port d. the stack pointer is set because there are push and pull instructions in the bootloader program. t he x index register is pointed at the start of the register block ($1000) so indexed addressing can be used. indexed addressing takes one less byte of rom space than extended instructions, and bit manipul ation instructions are not available in extended addressing forms. the port d wire-or mode (dwom) bit in the serial peripheral interface control register (spcr) is set to configure port d for wired-or operat ion to minimize potential conflicts with external systems that use the pd1/txd pin as an input. the baud rate for the sci is initially set to 7812 baud at a 2-mhz e-clock rate but can automatically switch to 1200 baud based on the first character received. the sci receiver and transmitter are enabled. the receiv er is required by the bootloading process, and the transmitter is used to transmit data back to the host co mputer for optional verification. the last item in the initialization is to set an intercharacter delay cons tant used to terminate the download when the host computer stops sending data to the mc68hc711e9. this delay constant is stored in the timer output compare 1 (toc1) register, but the on-chip timer is not used in the bootloader program. this example start $ff character @ 7812 baud [6] bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 7 bit 6 stop tx data line idles high start $ff character @ 1200 baud bit 0 bit 1 01 s 11111111 rx data samples 00 s 0000?111 rx data samples ( for 7812 baud ) $ff $c0 or $e0 [12] [1] [2] [3] [4] [5] [7] [9] [ 10 ] [11] [8]
main bootloader program m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 199 illustrates the extreme measures used in the bootl oader firmware to minimize memory usage. however, such measures are not usually considered good programming technique because they are misleading to someone trying to understand the program or use it as an example. after initialization, a break charac ter is transmitted [3] by the sci. by connecting the txd pin to the rxd pin (with a pullup because of port d wired-or mode), th is break will be received as a $00 character and cause an immediate jump [4] to the start of t he on-chip eeprom ($b600 in the mc68hc711e9). this feature is useful to pass control to a program in eeprom essentially from reset. refer to common bootstrap mode problems before using this feature. if the first character is received as $ff, the baud rate is assumed to be the default rate (7812 baud at a 2-mhz e-clock rate). if $ff was sent at 1200 baud by the host, the sci will receive the character as $e0 or $c0 because of the baud rate mismatch, and the bootloader will switch to 1200 baud [5] for the rest of the download operation. when the baud rate is switched to 1200 baud, the delay constant used to monitor the intercharacter delay also must be ch anged to reflect the new character time. at [6], the y index register is initialized to $0000 to poi nt to the start of on-chip ram. the index register y is used to keep track of where the next received data byte will be stored in ram. the main loop for loading begins at [7]. the number of data bytes in the downloaded program can be any number between 0 and 512 bytes (the size of on-chip ram). this procedure is called "var iable-length download" and is accomplished by ending the download sequence when an idle time of at least four character times occurs after the last character to be downloaded. in m68hc11 family members wh ich have 256 bytes of ram, the download length is fixed at exactly 256 bytes plus the leading $ff character. the intercharacter delay counter is started [8] by load ing the delay constant from toc1 into the x index register. the 19-e-cycle wait loop is executed repeatedl y until either a character is received [9] or the allowed intercharacter delay time expires [10]. for 7 812 baud, the delay constant is 10,241 e cycles (539 x 19 e cycles per loop). four character times at 7812 baud is 10,240 e cycles (baud prescale of 4 x baud divider of 4 x 16 internal sci clocks/bit time x 10 bi t times/character x 4 character times). the delay from reset to the initial $ff character is not critical since the delay counter is not started until after the first character ($ff) is received. to terminate the bootloading sequence and jump to t he start of ram without downloading any data to the on-chip ram, simply send $ff and nothing else. this feature is similar to the jump to eeprom at [4] except the $ff causes a jump to the start of ram. this procedure requires that the ram has been loaded with a valid program since it would make no sens e to jump to a location in uninitialized memory. after receiving a character, the downloaded byte is stored in ram [11]. the data is transmitted back to the host [12] as an indication that the download is progressing normally. at [13], the ram pointer is incremented to the next ram address. if the ram poi nter has not passed the end of ram, the main download loop (from [7] to [14]) is repeated. when all data has been downloaded, the bootloader goes to [16] because of an intercharacter delay timeout [10] or because the entire 512-byte ram has been filled [15]. at [16], the x and y index registers are set up for calling the program utility routine, which saves the user from having to do this in a downloaded program. the program utility is fully explained in eprom programming utility . the final step of the bootloader program is to jump to the start of ram [17], which starts the user?s downloaded program.
m68hc11 bootstrap mode, rev. 1.1 200 freescale semiconductor main bootloader program figure 3. mc68hc711e9 bootloader flowchart receive data ready ? initialization: sp = top of ram ($01ff) x = start of regs ($1000) spcr = $20 (set dwom bit) baud = $a2 ( 4; 4) (7812.5 baud @ 2 mhz) sccr2 = $c0 (tx & rx on) toc1 = delay constant (539 = 4 sci character times) start from reset in boot mode send break received first char yet ? no yes first char = $00 ? no yes jump to start of eeprom ($b600) notzero first char = $ff ? no yes baudok switch to slower sci rate... baud = $33 (13; 8) (1200 baud @ 2 mhz) change delay constant... toc1 = 3504 (4 sci character times) note that a break character is also received as $00 point to start of ram ( y = $0000 ) initialize timeout count store received data to ram ( ,y ) transmit (echo) for verify point at next ram location set up for program utility: x = programming time constant y = start of eprom jump to start of ram ($0000) wait no yes wtloop decrement timeout count timed out yet ? no yes past end of ram ? no yes star loop = 19 cycles [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
upload utility m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 201 upload utility the upload utility subroutine transfers data from the mcu to a host computer system over the sci serial data link. note only eprom versions of the m6 8hc11 include this utility. verification of eprom contents is one example of how the upload utility could be used. before calling this program, the y index register is loaded (by user firmware) with the address of the first data byte to be uploaded. if a baud rate other than the current sci baud rate is to be used for the upload process, the user?s firmware must also write to the baud regist er. the upload program sends successive bytes of data out the sci transmitter until a reset is issued (the upload loop is infinite). for a complete commented listing example of the upload utility, refer to listing 3. mc68hc711e9 bootloader rom . eprom programming utility the eprom programming utility is one way of progr amming data into the internal eprom of the mc68hc711e9 mcu. an external 12-v programming power supply is required to program on-chip eprom. the simplest way to use this utility program is to bootload a 3-byte program consisting of a single jump instruction to the start of the program utility program ($bf00). the bootloader program sets the x and y index registers to default values before jumping to the downloaded program (see [16] at the bottom of figure 3 ). when the host computer sees the $ff character, data to be programmed into the eprom is sent, starting with the character for locati on $d000. after the last byte to be programmed is sent to the mc68hc711e9 and the corresponding ve rification data is returned to the host, the programming operation is terminated by resetting the mcu. the number of bytes to be programmed, the first addr ess to be programmed, and the programming time can be controlled by the user if values other than the default values are desired. to understand the detailed operation of the eprom programming utility, refer to figure 4 during the following discussion. figure 4 is composed of three interrelated pa rts. the upper-left portion shows the flowchart of the program utility running in the boot rom of the mcu. the upper-right portion shows the flowchart for the user-supplied driver program running in the host computer. the lower portion of figure 4 is a timing sequence showing the relationship of operations between the mcu and the host computer. reference numbers in the flowcharts in the upper half of figure 4 have matching numbers in the lower half to help the reader relate the three parts of the figure. the shaded area [1] refers to the software and hardware latency in the mcu leading to the transmission of a character (in this case, the $ff). the shaded area [2] refers to a similar latency in the host computer (in this case, leading to the transmission of the first data character to the mcu). the overall operation begins when the mcu sends t he first character ($ff) to the host computer, indicating that it is ready for the first data charac ter. the host computer sends the first data byte [3] and enters its main loop. the second data character is sent [4], and the host then waits [5] for the first verify byte to come back from the mcu.
m68hc11 bootstrap mode, rev. 1.1 202 freescale semiconductor eprom programming utility figure 4. host and mcu activity duri ng eprom program utility d1 $ff p1 d2 v1 p2 v2 d3 p3 d4 v3 p4 v4 d5 eprom programming mcu receive data (from host) mcu transmit data (verify) $ff v1 v2 v3 v4 verify data to host (same as mcu tx data) mc68hc711e9 executing "program" loop host sending data for mcu eprom [3] [4] [5] [6] [1] [2] [7] [8] [9] [10] [11] [12] [13] [14] [15] send $ff start initialize... x = program time y = first address $bf00 - program wait1 any data received ? no yes program byte read programmed data and send to verify point to next location to be programmed indicates ready to host send first data byte start host normally waits for $ff from mcu before sending data for eprom programming data_loop more data to send ? no yes send next data indicate error verify data received ? no yes verify data correct ? no yes more to verify ? no yes done program continues as long as data is received [8] [9] [10] [11] [12] [13] [14] [15] [3] [4] [5] [6] [7] program utility in mcu driver program in host
allowing for bootstrap mode m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 203 after the mcu sends $ff [8], it enters the wait1 loop [9] and waits for the first data character from the host. when this character is received [10], the mcu pr ograms it into the address pointed to by the y index register. when the programming time delay is over, the mcu reads the programmed data, transmits it to the host for verification [11], and retu rns to the top of the wait1 loop to wait for the next data character [12]. because the host previously sent the second data c haracter, it is already waiting in the sci receiver of the mcu. steps [13], [14], and [15] correspond to the second pass through the wait1 loop. back in the host, the first verify character is rece ived, and the third data character is sent [6]. the host then waits for the second verify character [7] to come back from the mcu. the sequence continues as long as the host continues to send data to the mcu. since the wait1 loop in the program utility is an indefinite loop, reset is used to end the process in th e mcu after the host has finished sending data to be programmed. allowing for bootstrap mode since bootstrap mode requires few connections to the mcu, it is easy to design systems that accommodate bootstrap mode. bootstrap mode is useful for diagnosing or repairi ng systems that have failed due to changes in the config register or failures of the expansion a ddress/data buses, (rendering programs in external memory useless). bootstrap mode can also be used to load information into the eprom or eeprom of an m68hc11 after final assembly of a module. bootstrap mode is also useful for performing system checks and calibration routines. the following par agraphs explain system requirements for use of bootstrap mode in a product. mode select pins it must be possible to force the moda and modb pins to logic 0, which implies th at these two pins should be pulled up to v dd through resistors rather than being tied directly to v dd . if mode pins are connected directly to v dd , it is not possible to force a mode other th an the one the mcu is hard wired for. it is also good practice to use pulldown resistors to v ss rather than connecting mode pins directly to v ss because it is sometimes a useful debug aid to attempt reset in modes other than the one the system was primarily designed for. physically, this requirement sometimes calls for the addition of a test point or a wire connected to one or both mode pins. mode sele ction only uses the mode pins while reset is active. reset it must be possible to initiate a reset while the mode select pins are held low. in systems where there is no provision for manual reset, it is usually possibl e to generate a reset by turning power off and back on. rxd pin it must be possible to drive the pd0/rxd pin with serial data from a host computer (or another mcu). in many systems, this pin is already used for sci communications; thus no changes are required.
m68hc11 bootstrap mode, rev. 1.1 204 freescale semiconductor allowing for bootstrap mode in systems where the pd0/rxd pin is normally used as a general-purpose output, a serial signal from the host can be connected to the pin without resulting in output driver conflicts. it may be important to consider what the existing logic will do wi th the sci serial data instead of the signals that would have been produced by the pd0 pin. in systems where the pd 0 pin is used normally as a general-purpose input, the driver circuit that drives the pd0 pi n must be designed so that the serial data can override this driver, or the driver must be disconnected during the bootstr ap download. a simple series resistor between the driver and the pd0 pin solves this problem as shown in figure 5 . the serial data from the host computer can then be connected to the pd0/rxd pin, and the seri es resistor will prevent direct conflict between the host driver and the normal pd0 driver. figure 5. preventing driver conflict txd pin the bootloader program uses the pd1/txd pin to send verification data back to the host computer. to minimize the possibility of conflict s with circuitry connected to this pi n, port d is configured for wire-or mode by the bootloader program during initialization. since the wire-o r configuration prevents the pin from driving active high levels, a pullup resistor to v dd is needed if the txd signal is used. in systems where the pd1/txd pin is normally used as a general-purpose output, there are no output driver conflicts. it may be important to consider what the existing logic will do with the sci serial data instead of the signals that woul d have been produced by the pd1 pin. in systems where the pd1 pin is nor mally used as a general- purpose input, the driver circuit that drives the pd1 pin must be designed so that the pd1/txd pin driver in the mcu can override this driver. a simple series resistor between the driver and the pd1 pin can solve this problem. the txd pin can then be configured as an output, and the series resistor will prev ent direct conflict between the internal txd driver and the external driver connected to pd1 through the series resistor. other the bootloader firmware sets the dwom control bi t, which configures all port d pins for wire-or operation. during the bootloading process, all port d pins except the pd1/txd pin are configured as high-impedance inputs. any port d pin that normally is used as an output should have a pullup resistor so it does not float during the bootloading process. rxd/pd0 (being used as input) existing control signal series resistor rs232 level shifter from host system mc68hc11 existing driver connected only during bootloading
driving boot mode from another m68hc11 m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 205 driving boot mode from another m68hc11 a second m68hc11 system can eas ily act as the host to drive boot strap loading of an m68hc11 mcu. this method is used to examine and program non-vo latile memories in target m68hc11s in freescale evms. the following hardware and software exampl e will demonstrate this and other bootstrap mode features. the schematic in figure 6 shows the circuitry for a simple eprom duplicator for the mc68hc711e9. the circuitry is built in the wire-wrap area of an m68hc1 1evbu evaluation board to si mplify construction. the schematic shows only the important portions of the evbu circuitry to avoid confusion. to see the complete evbu schematic, refer to the m68hc11evbu universal eval uation board user?s manual , freescale document order number m68hc11evbu/d. the default configuratio n of the evbu must be changed to make the appropriate connections to the circuitry in the wire-wrap area and to configure t he master mcu for bootstrap mode. a fabricated jumper must be installed at j6 to connect the xtal output of the master mcu to the wire-wrap connector p5, which has been wired to the extal input of the target mcu. cut traces that short across j8 and j9 must be cut on the solder side of the printed circuit boar d to disconnect the normal sci connections to the rs232 level translator (u4) of the evbu. the j8 and j9 connections can be restored easily at a later time by installing fabricated jumpers on the component side of the board. a fabricated jumper must be installed across j3 to configure the master mcu for bootstrap mode. one mc68hc711e9 is first programmed by other mean s with a desired 12-kbyte program in its eprom and a small duplicator program in its eeprom. alternately, the rom program in an mc68hc11e9 can be copied into the eprom of a target mc68hc711e9 by programming only the duplicator program into the eeprom of the master mc68hc11e9. the master mcu is installed in the evbu at socket u3. a blank mc68hc711e9 to be programmed is placed in the socket in t he wire-wrap area of the evbu (u6). with the v pp power switch off, power is applied to the evbu system. as power is applied to the evbu, the master mcu (u3) comes out of reset in bootstrap mode. target mcu (u6) is held in reset by the pb7 output of master mcu (u3). the pb7 output of u3 is forced to 0 when u3 is reset. the master mcu will later release the reset signal to the target mcu under software control. the rxd and txd pins of the target mcu (u6) are high-impedance inputs while u6 is in re set so they will not affect the txd and rxd signals of the master mcu (u3) while u3 is coming out of re set. since the target mcu is being held in reset with moda and modb at 0, it is configured for th e prog eprom emulation mode, and pb7 is the output enable signal for the eprom data i/o (input/output) pins. pullup resistor r7 causes the port d pins, including rxd and txd, to remain in the high-impedance state so they do not interfere with the rxd and txd pins of the master mcu as it comes out of reset. as u3 leaves reset, its mode pins select bootstra p mode so the bootloader firmware begins executing. a break is sent out the txd pin of u3. pullup resistor r10 and resistor r9 cause the break character to be seen at the rxd pin of u3. the bootloader performs a jump to the start of eeprom in the master mcu (u3) and starts executing the duplicator program. this sequence demonstrates how to use bootstrap mode to pass control to the start of eeprom after reset. the complete listing for the duplicator program in the eeprom of the master mcu is provided in listing 1. mcu-to-mcu duplicator program .
m68hc11 bootstrap mode, rev. 1.1 206 freescale semiconductor driving boot mode fr om another m68hc11 figure 6. mcu-to -mcu eprom duplicator schematic 100 r11 off on v pp s2 + c18 20 f r14 15k r15 10k 1k r12 red d5 1k r13 green d6 v dd c17 0.1 f 3.3k r8 j8 j9 r10 15k r9 10k v dd v dd 10k r7 pb7 rxd extal txd moda modb v dd v ss xirq/v ppe reset mc68hc711e9 target mcu u6 j6 j3 to/from rs232 level translator u4 pb7 rxd xtal txd modb pb0 pb1 pe7 17 21 7 20 1 26 35 20 8 21 42 41 50 18 35 3 2 35 20 8 21 42 41 50 +12.25v com p5 p4 wire-wrap area m68hc11evbu prewired area 35 20 8 21 42 41 50 2 master mcu u3 [1] [2]
driving boot mode from another m68hc11 m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 207 the duplicator program in eeprom cl ears the dwom control bit to c hange port d (thus, txd) of u3 to normal driven outputs. this configur ation will prevent interference due to r9 when txd from the target mcu (u6) becomes active. series resistor r9 demon strates how txd of u3 can drive rxd of u3[1] and later txd of u6 can drive rxd of u3 without a destructive conflict between the txd output buffers. as the target mcu (u6) leaves reset, its mode pi ns select bootstrap mode so the bootloader firmware begins executing. a break is sent out the txd pin of u6 . at this time, the txd pin of u3 is at a driven high so r9 acts as a pullup resistor for txd of the tar get mcu (u6). the break character sent from u6 is received by u3 so the duplicator program that is running in the eeprom of the master mcu knows that the target mcu is ready to accept a bootloaded program. the master mcu sends a leading $ff character to set the baud rate in the target mcu. next, the master mcu passes a 3-instruction program to the target mcu and pauses so the bootstrap program in the target mcu will stop the loading process and jump to the start of the downloaded program. this sequence demonstrates the variable-length download fe ature of the mc68hc711e9 bootloader. the short program downloaded to the target mcu clears the dwom bit to change its txd pin to a normal driven cmos output and jumps to the eprom programming utility in the bootstrap rom of the target mcu. note that the small downloaded program did not have to set up the sci or initialize any parameters for the eprom programming process. the bootstrap software that ran prior to the loaded program left the sci turned on and configured in a way that was compatible with the sci in the master mcu (the duplicator program in the master mcu also did not have to set up the sci for the same reason). the programming time and starting address for eprom programming in the target mcu were also set to default values by the bootloader software before jumping to the start of the downloaded program. before the eprom in the target mcu can be programmed, the v pp power supply must be available at the xirq /v ppe pin of the target mcu. the duplicator program running in the master mcu monitors this voltage (for presence or absence, not level) at pe7 through resistor divider r14?rl5. the pe7 input was chosen because the internal circuitry for port e pins can tolerate voltages slightly higher than v dd ; therefore, resistors r14 and r15 are less critical. no data to be programmed is passed to the target mcu until the master mcu senses that v pp has been stable for about 200 ms. when v pp is ready, the master mcu turns on the red le d (light-emitting diode) and begins passing data to the target mcu. eprom programming utility explains the activity as data is sent from the master mcu to the target mcu and programmed into the eprom of the target. the master mcu in the evbu corresponds to the host in the programming utility description and the "program utility in mcu" is running in the bootstrap rom of the target mcu. each byte of data sent to the target is programmed and then the programmed location is read and sent back to the master for verification. if any byte fail s, the red and green leds are turned off, and the programming operation is aborted. if the entire 12 kb ytes are programmed and verified successfully, the red led is turned off, and the green led is turned on to indicate success. the programming of all 12 kbytes takes about 30 seconds. after a programming operation, the v pp switch (s2) should be turned o ff before the evbu power is turned off.
m68hc11 bootstrap mode, rev. 1.1 208 freescale semiconductor listing 1. mcu-to-mcu duplicator program figure 7. isol ating evbu xirq pin listing 1. mcu-to-mcu duplicator program 1 ************************************************** 2 * 68hc711e9 duplicator program for an1060 3 ************************************************** 4 5 ***** 6 * equates - all reg addrs except init are 2-digit 7 * for direct addressing 8 ***** 9 103d init equ $103d ram, reg mapping 10 0028 spcr equ $28 dwom in bit-5 11 0004 portb equ $04 red led = bit-1, grn = bit-0 12 * reset of prog socket = bit-7 13 0080 reset equ %10000000 14 0002 red equ %00000010 15 0001 green equ %00000001 16 000a porte equ $0a vpp sense in bit-7, 1=on 17 002e scsr equ $2e sci status register 18 * tdre, tc, rdrf, idle; or, nf, fe, - 19 0080 tdre equ %10000000 20 0020 rdrf equ %00100000 21 002f scdr equ $2f sci data register 22 bf00 program equ $bf00 eprom prog utility in boot rom 23 d000 epstrt equ $d000 starting address of eprom 24 25 b600 org $b600 start of eeprom 26 25 13 1 1 1 3 + 9 8 10 20 21 19 15 7 1 2 45 48 47 46 44 41 38 34 35 33 27 28 42 50 cut trace as shown rn1d 47k v dd j14 j7 to mc68hc68t1 remove j7 jumper be sure no jumper is on j14 from oc5 pin of mcu to mcu x i r q / v pin ppe p4-18 p5-18 to mcu xirq /v ppe pin
listing 1. mcu-to-mcu duplicator program m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 209 27 ************************************************** 28 * 29 b600 7f103d begin clr init moves registers to $0000-3f 30 b603 8604 ldaa #$04 pattern for dwom off, no spi 31 b605 9728 staa spcr turns off dwom in evbu mcu 32 b607 8680 ldaa #reset 33 b609 9704 staa portb release reset to target mcu 34 b60b 132e20fc wt4brk brclr scsr rdrf wt4brk loop till char received 35 b60f 86ff ldaa #$ff leading char for bootload ... 36 b611 972f staa scdr to target mcu 37 b613 ceb675 ldx #blprog point at program for target 38 b616 8d53 blloop bsr send1 bootload to target 39 b618 8cb67d cpx #endbpr past end ? 40 b61b 26f9 bne blloop continue till all sent 41 ***** 42 * delay for about 4 char times to allow boot related 43 * sci communications to finish before clearing 44 * rx related flags 45 b61d ce06a7 ldx #1703 # of 6 cyc loops 46 b620 09 dlylp dex [3] 47 b621 26fd bne dlylp [3] total loop time = 6 cyc 48 b623 962e ldaa scsr read status (rdrf will be set) 49 b625 962f ldaa scdr read sci data reg to clear rdrf 50 ***** 51 * now wait for character from target to indicate it's ready for 52 * data to be programmed into eprom 53 b627 132e20fc wt4ff brclr scsr rdrf wt4ff wait for rdrf 54 b62b 962f ldaa scdr clear rdrf, don't need data 55 b62d ced000 ldx #epstrt point at start of eprom 56 * handle turn-on of vpp 57 b630 18ce523d wt4vpp ldy #21053 delay counter (about 200ms) 58 b634 150402 bclr portb red turn off red led 59 b637 960a dlylp2 ldaa porte [3] wait for vpp to be on 60 b639 2af5 bpl wt4vpp [3] vpp sense is on port e msb 61 b63b 140402 bset portb red [6] turn on red led 62 b63e 1809 dey [4] 63 b640 26f5 bne dlylp2 [3] total loop time = 19 cyc 64 * vpp has been stable for 200ms 65 66 b642 18ced000 ldy #epstrt x=tx pointer, y=verify pointer 67 b646 8d23 bsr send1 send first data to target 68 b648 8c0000 datalp cpx #0 x points at $0000 after last 69 b64b 2702 beq verf skip send if no more 70 b64d 8d1c bsr send1 send another data char 71 b64f 132e20fc verf brclr scsr rdrf verf wait for rx ready 72 b653 962f ldaa scdr get char and clr rdrf 73 b655 18a100 cmpa 0,y does char verify ? 74 b658 2705 beq verfok skip error if ok 75 b65a 150403 bclr portb (red+green) turn off leds 76 b65d 2007 bra dunprg done (programming failed) 77 b65f 78 b65f 1808 verfok iny advance verify pointer 79 b661 26e5 bne datalp continue till all done 80 b663 81 b663 140401 bset portb green grn led on
m68hc11 bootstrap mode, rev. 1.1 210 freescale semiconductor listing 1. mcu-to-mcu duplicator program 82 b666 83 b666 150482 dunprg bclr portb (reset+red) red off, apply reset 84 b669 20fe bra * done so just hang 85 b66b 86 ************************************************** 87 * subroutine to get & send an sci char. also 88 * advances pointer (x). 89 ************************************************** 90 b66b a600 send1 ldaa 0,x get a character 91 b66d 132e80fc trdylp brclr scsr tdre trdylp wait for tdre 92 b671 972f staa scdr send character 93 b673 08 inx advance pointer 94 b674 39 rts ** return ** 95 96 ************************************************** 97 * program to be bootloaded to target '711e9 98 ************************************************** 99 b675 8604 blprog ldaa #$04 pattern for dwom off, no spi 100 b677 b71028 staa $1028 turns off dwom in target mcu 101 * note: can't use direct addressing in target mcu because 102 * regs are located at $1000. 103 b67a 7ebf00 jmp program jumps to eprom prog routine 104 b67d endbpr equ * symbol table: symbol name value def.# line number cross reference begin b600 *00029 blloop b616 *00038 00040 blprog b675 *00099 00037 datalp b648 *00068 00079 dlylp b620 *00046 00047 dlylp2 b637 *00059 00063 dunprg b666 *00083 00076 endbpr b67d *00104 00039 epstrt d000 *00023 00055 00066 green 0001 *00015 00075 00081 init 103d *00009 00029 portb 0004 *00011 00033 00058 00061 00075 00081 00083 porte 000a *00016 00059 program bf00 *00022 00103 rdrf 0020 *00020 00034 00053 00071 red 0002 *00014 00058 00061 00075 00083 reset 0080 *00013 00032 00083 scdr 002f *00021 00036 00049 00054 00072 00092 scsr 002e *00017 00034 00048 00053 00071 00091 send1 b66b *00090 00038 00067 00070 spcr 0028 *00010 00031 tdre 0080 *00019 00091 trdylp b66d *00091 00091 verf b64f *00071 00069 00071 verfok b65f *00078 00074 wt4brk b60b *00034 00034 wt4ff b627 *00053 00053 wt4vpp b630 *00057 00060
driving boot mode from a personal computer m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 211 errors: none labels: 28 last program address: $b67c last storage address: $0000 program bytes: $007d 125 storage bytes: $0000 0 driving boot mode fr om a personal computer in this example, a personal computer is used as the host to drive the bootloader of an mc68hc711e9. an m68hc11 evbu is used for the target mc68hc 711e9. a large program is transferred from the personal computer into the eprom of the target mc68hc711e9. hardware figure 7 shows a small modification to the evbu to accommodate the 12-volt (nominal) eprom programming voltage. the xirq pin is connected to a pullup resistor, two jumpers, and the 60-pin connectors, p4 and p5. the object of the modification is to isolate the xirq pin and then connect it to the programming power supply. carefully cut the trace on the solder side of the evbu as indicated in figure 7 . this disconnects the pullup resistor rn1 d from xirq but leaves p4?18, p5?18, and jumpers j7 and j14 connected so the evbu c an still be used for other purposes afte r programming is done. remove any fabricated jumpers from j7 and j14. the evbu normally has a jumper at j7 to support the trace function figure 8 shows a small circuit that is added to the wire-w rap area of the evbu. the 3-terminal jumper allows the xirq line to be connected to either the programming power supply or to a substitute pullup resistor for xirq . the 100-ohm resistor is a current limiter to protect the 12-volt input of the mcu. the resistor and led connected to p5 pin 9 (port c bit 0) is an optional indicator that lights when programming is complete. software basic was chosen as the programming language due to it s readability and availabilit y in parallel versions on both the ibm ? pc and the macintosh ? . the program demonstrates several programming techniques for use with an m68hc11 and is not necessarily intended to be a finished, commercial program. for example, there is little error checking, and the user interface is elementary. a complete listing of the basic program is included in listing 2. basic program for personal computer with moderate comments. the following paragraphs include a more detailed di scussion of the program as it pertains to communicating with and programming the target mc 68hc711e9. lines 25?45 initialize and define the variables and array used in the program. changes to this section would allow for other programs to be downloaded. ? ibm is a registered trademark of international business machines. ? macintosh is a registered tradem ark of apple computers, inc.
m68hc11 bootstrap mode, rev. 1.1 212 freescale semiconductor driving boot mode from a personal computer figure 8. pc-to-mcu programming circuit lines 50?95 read in the small bootloader from data st atements at the end of the listing. the source code for this bootloader is presented in the data statements. the bootloaded code makes port c bit 0 low, initializes the x and y registers for use by the eprom programming utility routine contained in the boot rom, and then jumps to that routine. the hexade cimal values read in from the data statements are converted to binary values by a subroutine. the binary values are then saved as one string (bootcode$). the next long section of code (lines 97?1250) reads in th e s records from an external disk file (in this case, buf34.s19), converts them to integer, and save s them in an array. the techniques used in this section show how to convert ascii s records to binary form that can be sent (bootloaded) to an m68hc11. this s-record translator only looks for the s1 records that contain the actual object code. all other s-record types are ignored. when an s1 record is found (lines 1000?1024), the next two characters form the hex byte giving the number of hex bytes to follow. this byte is converted to integer by the same subroutine that converted the bootloaded code from the data statements. this bytecount is adjusted by subtracting 3, which accounts for the address and checksum bytes and leaves just the number of object-code bytes in the record. starting at line 1100, the 2-byte (4-character) starting address is converted to decimal. this address is the starting address for the object code bytes to follow. an index into the code% array is formed by subtracting the base address initialized at the start of the program from the starting address for this s record. a for-next loop starting at line 1130 converts the obje ct code bytes to decimal and saves them in the code% array. when all the object code bytes have be en converted from the current s record, the program loops back to find the next s1 record. 100 normal evbu operation jumper + 20 f +12.25 v common programming power 47k v dd program eprom 1k pc0 p5-9 led to p5-18 (xirq/v ) ppe
driving boot mode from a personal computer m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 213 a problem arose with the basic programming technique us ed. the draft versions of this program tried saving the object code bytes directly as binary in a st ring array. this caused "out of memory" or "out of string space" errors on both a 2-mbyte macintosh and a 640-kbyte pc. the solution was to make the array an integer array and perform the integer-to-binary c onversion on each byte as it is sent to the target part. the one compromise made to accommodate both macintosh and pc versions of basic is in lines 1500 and 1505. use line 1500 and comment out line 1505 if the program is to be run on a macintosh, and, conversely, use line 1505 and comment out line 1500 if a pc is used. after the com port is opened, the code to be bootloaded is modified by adding the $ff to the start of the string. $ff synchronizes the bootloader in the mc68hc711e9 to 1200 baud. the entire string is simply sent to the com port by printing the string. this is possible since the st ring is actually queued in basic?s com buffer, and the operating system takes care of sending the byte s out one at a time. the m68hc11 echoes the data received for verification. no automatic verification is provided, though the data is printed to the screen for manual verification. once the mcu has received this bootloaded code, the bootloader automatically jumps to it. the small bootloaded program in turn includes a jump to the eprom programming routine in the boot rom. refer to the previous explanation of the eprom programming utility for the following discussion. the host system sends the first byte to be programmed through the com port to the sci of the mcu. the sci port on the mcu buffers one byte while receiving another byte, increasing the throughput of the eprom programming operation by sending the second by te while the first is being programmed. when the first byte has been programmed, the mcu r eads the eprom location and sends the result back to the host system. the host then compares what was actually programmed to what was originally sent. a message indicating which byte is bei ng verified is displayed in the lower half of the screen. if there is an error, it is displayed at the top of the screen. as soon as the first byte is verified, the third byte is sent. in the meantime, the mcu has already started programming the second byte. this process of veri fying and queueing a byte continues until the host finishes sending data. if the programming is co mpletely successful, no error messages will have been displayed at the top of the screen. subroutines follow the end of the program to handle some of the repetitive tasks. these routines are short, and the commenting in the source code should be sufficient explanation. modifications this example programmed version 3.4 of the buffa lo monitor into the eprom of an mc68hc711e9; the changes to the basic program to download some other program are minor. the necessary changes are: 1. in line 30, the length of the program to be downloaded must be assigned to the variable codesize%. 2. also in line 30, the starting address of the program is assigned to the variable adrstart. 3. in line 9570, the start address of the program is stored in the third and fourth items in that data statement in hexadecimal. 4. if any changes are made to the number of bytes in the boot code in the data statements in lines 9500?9580, then the new count must be set in the variable "bootcount" in line 25.
m68hc11 bootstrap mode, rev. 1.1 214 freescale semiconductor driving boot mode from a personal computer operation configure the evbu for boot mode operation by putti ng a jumper at j3. ensure that the trace command jumper at j7 is not installed because this would connect the 12-v programming voltage to the oc5 output of the mcu. connect the evbu to its dc power supply. when it is time to program the mcu eprom, turn on the 12-volt programming power supply to the new circuitry in the wire-wrap area. connect the evbu serial port to the appropriate serial port on the host system. for the macintosh, this is the modem port with a modem cable. for the ms-dos ? computer, it is connected to com1 with a straight through or modem cable. power up the host system and start the basic program. if the program has not been compiled, this is acco mplished from within the appropriate basi c compiler or inte rpreter. power up the evbu. answer the prompt for filename with either a [return] to accept the default shown or by typing in a new filename and pressing [return]. the program will inform the user that it is working on converting the file from s records to binary. this process will take from 30 seconds to a few minutes, depending on the computer. a prompt reading, "comm port open?" will appear at the end of the file conversion. this is the last chance to ensure that everything is properly configured on the evbu. pressing [return] will send the bootcode to the target mc68hc711e9. the program then informs the user that the bootload code is being sent to the target, and the results of the echoing of this code are displayed on the screen. another prompt reading "programming is ready to begin. are you?" will appear. turn on the 12-volt programming power supply and press [return] to st art the actual programmi ng of the target eprom. a count of the byte being verified will be updated continually on the screen as the programming progresses. any failures will be flagged as they occur. when programming is complete, a message will be displa yed as well as a prompt requesting the user to press [return] to quit. turn off the 12-volt program ming power supply before turning off 5 volts to the evbu. ? ms-dos is a registered trademark of microsoft corporation in the unit ed states and oth175190er countries.
listing 2. basic program for personal computer m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 215 listing 2. basic progra m for personal computer 1 ' *********************************************************************** 2 ' * 3 ' * e9buf.bas - a program to demonstrate the use of the boot mode 4 ' * on the hc11 by programming an hc711e9 with 5 ' * buffalo 3.4 6 ' * 7 ' * requires that the s-records for buffalo (buf34.s19) 8 ' * be available in the same directory or folder 9 ' * 10 '* this program has been run both on a ms-dos computer 11 '* using quickbasic 4.5 and on a macintosh using 12 '* quickbasic 1.0. 14 '* 15 '************************************************************************ 25 h$ = "0123456789abcdef" 'string to use for hex conversions 30 defint b, i: codesize% = 8192: adrstart= 57344! 35 bootcount = 25 'number of bytes in boot code 40 dim code%(codesize%) 'buffalo 3.4 is 8k bytes long 45 bootcode$ = "" 'initialize bootcode$ to null 49 rem ***** read in and save the code to be boot loaded ***** 50 for i = 1 to bootcount '# of bytes in boot code 55 read q$ 60 a$ = mid$(q$, 1, 1) 65 gosub 7000 'converts hex digit to decimal 70 temp = 16 * x 'hang on to upper digit 75 a$ = mid$(q$, 2, 1) 80 gosub 7000 85 temp = temp + x 90 bootcode$ = bootcode$ + chr$(temp) 'build boot code 95 next i 96 rem ***** s-record conversion starts here ***** 97 filnam$="buf34.s19" 'default file name for s-records 100 cls 105 print "filename.ext of s-record file to be downloaded (";filnam$;") "; 107 input q$ 110 if q$<>"" then filnam$=q$ 120 open filnam$ for input as #1 130 print : print "converting "; filnam$; " to binary..." 999 rem ***** scans for 's1' records ***** 1000 gosub 6000 'get 1 character from input file 1010 if flag then 1250 'flag is eof flag from subroutine 1020 if a$ <> "s" then 1000 1022 gosub 6000 1024 if a$ <> "1" then 1000 1029 rem ***** s1 record found, next 2 hex digits are the byte count ***** 1030 gosub 6000 1040 gosub 7000 'returns decimal in x 1050 bytecount = 16 * x 'adjust for high nibble 1060 gosub 6000 1070 gosub 7000 1080 bytecount = bytecount + x 'add low nibble
m68hc11 bootstrap mode, rev. 1.1 216 freescale semiconductor listing 2. basic program for personal computer 1090 bytecount = bytecount - 3 'adjust for address + checksum 1099 rem ***** next 4 hex digits become the starting address for the data ***** 1100 gosub 6000 'get first nibble of address 1102 gosub 7000 'convert to decimal 1104 address= 4096 * x 1106 gosub 6000 'get next nibble 1108 gosub 7000 1110 address= address+ 256 * x 1112 gosub 6000 1114 gosub 7000 1116 address= address+ 16 * x 1118 gosub 6000 1120 gosub 7000 1122 address= address+ x 1124 arraycnt = address-adrstart 'index into array 1129 rem ***** convert the data digits to binary and save in the array ***** 1130 for i = 1 to bytecount 1140 gosub 6000 1150 gosub 7000 1160 y = 16 * x 'save upper nibble of byte 1170 gosub 6000 1180 gosub 7000 1190 y = y + x 'add lower nibble 1200 code%(arraycnt) = y 'save byte in array 1210 arraycnt = arraycnt + 1 'increment array index 1220 next i 1230 goto 1000 1250 close 1 1499 rem ***** dump bootload code to part ***** 1500 'open "r",#2,"com1:1200,n,8,1" 'macintosh com statement 1505 open "com1:1200,n,8,1,cd0,cs0,ds0,rs" for random as #2 'dos com statement 1510 input "comm port open"; q$ 1512 while loc(2) >0 'flush input buffer 1513 gosub 8020 1514 wend 1515 print : print "sending bootload code to target part..." 1520 a$ = chr$(255) + bootcode$ 'add hex ff to set baud rate on target hc11 1530 gosub 6500 1540 print 1550 for i = 1 to bootcount '# of bytes in boot code being echoed 1560 gosub 8000 1564 k=asc(b$):gosub 8500 1565 print "character #"; i; " received = "; hx$ 1570 next i 1590 print "programming is ready to begin.": input "are you ready"; q$ 1595 cls 1597 while loc(2) > 0 'flush input buffer 1598 gosub 8020 1599 wend 1600 xmt = 0: rcv = 0 'pointers to xmit and receive bytes 1610 a$ = chr$(code%(xmt)) 1620 gosub 6500 'send first byte 1625 for i = 1 to codesize% - 1 'zero based array 0 -> codesize-1 1630 a$ = chr$(code%(i)) 'send second byte to get one in queue 1635 gosub 6500 'send it
listing 2. basic program for personal computer m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 217 1640 gosub 8000 'get byte for verification 1650 rcv = i - 1 1660 locate 10,1:print "verifying byte #"; i; " " 1664 if chr$(code%(rcv)) = b$ then 1670 1665 k=code%(rcv):gosub 8500 1666 locate 1,1:print "byte #"; i; " ", " - sent "; hx$; 1668 k=asc(b$):gosub 8500 1669 print " received "; hx$; 1670 next i 1680 gosub 8000 'get byte for verification 1690 rcv = codesize% - 1 1700 locate 10,1:print "verifying byte #"; codesize%; " " 1710 if chr$(code%(rcv)) = b$ then 1720 1713 k=code(rcv):gosub 8500 1714 locate 1,1:print "byte #"; codesize%; " ", " - sent "; hx$; 1715 k=asc(b$):gosub 8500 1716 print " received "; hx$; 1720 locate 8, 1: print : print "done!!!!" 4900 close 4910 input "press [return] to quit...", q$ 5000 end 5900 '*********************************************************************** 5910 '* subroutine to read in one byte from a disk file 5930 '* returns byte in a$ 5940 '*********************************************************************** 6000 flag = 0 6010 if eof(1) then flag = 1: return 6020 a$ = input$(1, #1) 6030 return 6490 '*********************************************************************** 6492 '* subroutine to send the string in a$ out to the device 6494 '* opened as file #2. 6496 '*********************************************************************** 6500 print #2, a$; 6510 return 6590 '*********************************************************************** 6594 '* subroutine that converts the hex digit in a$ to an integer 6596 '*********************************************************************** 7000 x = instr(h$, a$) 7010 if x = 0 then flag = 1 7020 x = x - 1 7030 return 7990 '********************************************************************** 7992 '* subroutine to read in one byte through the comm port opened 7994 '* as file #2. waits indefinitely for the byte to be 7996 '* received. subroutine will be aborted by any 7998 '* keyboard input. returns byte in b$. uses q$. 7999 '********************************************************************** 8000 while loc(2) = 0 'wait for comm port input 8005 q$ = inkey$: if q$ <> "" then 4900 'if any key pressed, then abort 8010 wend 8020 b$ = input$(1, #2) 8030 return 8490 '************************************************************************
m68hc11 bootstrap mode, rev. 1.1 218 freescale semiconductor common bootstrap mode problems 8491 '* decimal to hex conversion 8492 '* input: k - integer to be converted 8493 '* output: hx$ - two character string with hex conversion 8494 '************************************************************************ 8500 if k > 255 then hx$="too big":goto 8530 8510 hx$=mid$(h$,k\16+1,1) 'upper nibble 8520 hx$=hx$+mid$(h$,(k mod 16)+1,1) 'lower nibble 8530 return 9499 '******************** boot code **************************************** 9500 data 86, 23 'ldaa #$23 9510 data b7, 10, 02 'staa opt2 make port c wire or 9520 data 86, fe 'ldaa #$fe 9530 data b7, 10, 03 'staa portc light 1 led on port c bit 0 9540 data c6, ff 'ldab #$ff 9550 data f7, 10, 07 'stab ddrc make port c outputs 9560 data ce, 0f, a0 'ldx #4000 2msec at 2mhz 9570 data 18, ce, e0, 00 'ldy #$e000 start of buffalo 3.4 9580 data 7e, bf, 00 'jmp $bf00 eprom routine start address 9590 '*********************************************************************** common bootstrap mode problems it is not unusual for a user to encounter problems with bootstrap mode because it is new to many users. by knowing some of the common difficulties, the user can avoid them or at least recognize and quickly correct them. reset conditions vs. conditions as bootloaded program starts it is common to confuse the reset state of systems and control bits with the state of these systems and control bits when a bootloaded program in ram starts. between these times, the bootloader program is exec uted, which changes the states of some systems and control bits: the sci system is initialized and turned on (rx and tx). the sci system has control of the pd0 and pd1 pins. port d outputs are configured for wire-or operation. the stack pointer is initialized to the top of ram. time has passed (two or more sci character times). timer has advanced from its reset count value. users also forget that bootstrap mode is a special m ode. thus, privileged control bits are accessible, and write protection for some registers is not in effect. the bootstrap rom is in the memory map. the disr bit in the test1 control register is set, which disabl es resets from the cop and clock monitor systems. since bootstrap is a special mode, these conditions can be changed by software. the bus can even be switched from single-chip mode to expanded mode to gain access to external memories and peripherals.
an1060 ? rev. 1.0 motorola m68hc11 bootstrap mode 219 application note common bootstrap mode problems table 2. summary of boot-rom-related features mcu part boot rom revision (@$bfd1) mask set i.d. (@$bfd2,3) mcu type i.d. (@$bfd4,5) security download length jmp on brk or $00 (1) notes: 1. by sending $00 or a break as the first sci character after reset in bootstrap mode, a jump (jmp) is executed to the address in this table rather than doing a download. unless otherwise noted, this address is the start of eeprom. tying rxd to txd and using a pullup resistor fro m txd to v dd will cause the sci to see a break as the first received character. jmp to ram (2) 2. if $55 is received as the first character after reset in boot strap mode, a jump (j mp) is executed to the start of on-chip ra m rather than doing a download. this $55 character must be sent at the default baud rate (7812 baud @ e = 2 mhz). for devices with variable-length do wnload, the same effect can be achieved by sending $ff and no other sci characte rs. after four sci character time s, the download terminates, and a jump (jmp) to the start of ram is executed. the jump to ram feature is only useful if the ra m was previously loaded with a meaningful program. default ram location program (3) and upload (4) utility 3. a callable utility subroutine is include d in the bootstrap rom of the indicated versions to program bytes of on-chip eprom with data received via the sci. 4. a callable utility subroutine is included in the bootstrap rom of the indicated versions to upload contents of on-chip memor y to a host computer via the sci. notes mc68hc11a0 mc68hc11a1 mc68hc11a8 mc68sec11a8 ? ? ? ? ? ? ? ? mask set # mask set # mask set # mask set # ? ? ? ye s 256 256 256 256 $b600 $b600 $b600 $b600 $0000 $0000 $0000 $0000 $0000?ff $0000?ff $0000?ff $0000?ff ? ? ? ? (5) (5) (5) (5) 5. the complete listing for this b ootstrap rom may be found in the m68hc11 reference manual , freescale document order number m68hc11rm/ad. mc68hc11d3 mc68hc711d3 $00 $42(b) rom i.d. # $0000 $11d3 $71d3 ? ? 0?192 0?192 $f000?rom $f000?eprom ? ? $0040?ff $0040?ff ? ye s (6) (6) 6. the complete listing for this bootstrap rom is ava ilable in the freeware area of the freescale web site. mc68hc811e2 mc68sec811e2 ? ? $0000 ? $e2e2 $e25c ? ye s 256 256 $b600 $b600 $0000 $0000 $0000?ff $0000?ff ? ? (5) (5) mc68hc11e0 mc68hc11e1 mc68hc11e9 mc68sec11e9 ? ? ? ? rom i.d. # rom i.d. # rom i.d. # rom i.d. # $e9e9 $e9e9 $e9e9 $e95c ? ? ? ye s 0?512 0?512 0?512 0?512 $b600 $b600 $b600 $b600 ? ? ? ? $0000?1ff $0000?1ff $0000?1ff $0000?1ff ? ? ? ? (5) (5) (5) (5) mc68hc711e9 $41(a) $0000 $71e9 ? 0?512 $b600 ? $0000?1ff yes mc68hc11f1 $42(b) $0000 $f1f1 ? 0?1024 $fe00 ? $0000?3ff ? (6), (7) 7. due to the extra program spac e needed for eeprom security on this device, there are no pseudo-vectors for sci, spi, paif, pa ovf, tof, oc5f, or oc4f interrupts. mc68hc11k4 mc68hc711k4 $30(0) $42(b) rom i.d. # $0000 $044b $744b ? ? 0?768 0?768 $0d80 $0d80 ? ? $0080?37f $0080?37f ? ye s (6), (8) (6), (8) 8. this bootloader extends th e automatic software detection of baud rates to include 9600 baud at 2-mhz e-clock rate.
m68hc11 bootstrap mode, rev. 1.1 220 freescale semiconductor common bootstrap mode problems connecting rxd to v ss does not cause the sci to receive a break to force an immediate jump to the start of eeprom, the bootstrap firmware l ooks for the first received character to be $00 (or break). the data reception logic in the sci looks for a 1-to-0 transition on the rxd pin to synchronize to the beginning of a receive charac ter. if the rxd pin is tied to ground, no 1-to-0 transition occurs. the sci transmitte r sends a break character when the bootloader firmware starts, and this break character can be fed back to the rxd pin to cause the jump to eeprom. since txd is configured as an open-drain output, a pullup resistor is required. $ff character is required before loading into ram the initial character (usually $ff) that sets the download baud rate is often forgotten. original m68hc11 versions required exactly 256 bytes to be downloaded to ram even users that know about the 256 bytes of download data sometimes forget the initial $ff that makes the total number of bytes required for the entire download operation equal to 256 + 1 or 257 bytes. variable-length download when on-chip ram surpassed 256 bytes, the time requir ed to serially load this many characters became more significant. the variable-leng th download feature allows shorter programs to be loaded without sacrificing compatibility with earlier fixed-lengt h download versions of the bootloader. the end of a download is indicated by an idle rxd line for at least four character times. if a personal computer is being used to send the download data to the mcu, there can be problems keeping characters close enough together to avoid tripping the end-of-download detec t mechanism. using 1200 as the baud rate rather than the faster default rate may help this problem. assemblers often produce s-record encoded prog rams which must be converted to binary before bootloading them to the mcu. the process of reading s-record data from a file and translating it to binary can be slow, depending on the personal computer and the programming language used for the translation. one strategy that can be used to overcome this problem is to translate the file into binary and store it into a ram array before starting the download process. data can then be read and downloaded without the translation or file-read delays. the end-of-download mechanism goes into effect when the initial $ff is received to set the baud rate. any amount of time may pass between reset and when the $ff is sent to start the download process. eprom/otp versions of m68hc11 have an eprom emulation mode the conditions that configure the mcu for eprom emul ation mode are essentially the same as those for resetting the mcu in bootstrap mode. while reset is low and mode select pins are configured for bootstrap mode (low), the mcu is configured for eprom emulation mode. the port pins that are used for eprom data i/o lines may be inputs or outputs, depending on the pin that is emulating the eprom output enable pin (oe ). to make these data pins appear as high-impedance inputs as they would on a non-eprom part in reset, connect the pb7 /(oe ) pin to a pullup resistor.
boot rom variations m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 221 bootloading a program to performa rom checksum the bootloader rom must be turned off before performin g the checksum program. to remove the boot rom from the memory map, clear the rboot bit in t he hprio register. this is normally a write-protected bit that is 0, but in bootstrap mode it is reset to 1 and can be written. if the boot rom is not disabled, the checksum routine will read the contents of the boot rom rather than the user?s mask rom or eprom at the same addresses. inherent delays caused by double buffering of sci data this problem is troublesome in cases where one mcu is bootloading to another mcu. because of transmitter double buffering, there may be one character in the serial shifter as a new character is written into the transmit data register. in cases such as downloading in which this 2-character pipeline is kept full, a 2-character time delay occurs between when a character is written to the transmit data register and when that charac ter finishes transmitting. a little more than one more character time delay occurs between the target mcu receiving the character and echoing it back. if the master mcu waits for the echo of each downloaded character before sending the next one, the download process takes about twice as long as it would if transmission is treated as a separate process or if verify data is ignored. boot rom variations different versions of the m68hc11 have different versions of the bootstrap rom program. table 3 summarizes the features of the boot roms in 16 members of the m68hc11 family. the boot roms for the mc68hc11f1, the mc 68hc711k4, and the mc68hc11k4 allow additional choices of baud rates for bootloader communications. for the three new baud rates, the first character used to determine the baud rate is not $ff as it was in earlier m68hc11s. the intercharacter delay that terminates the variable-length download is also different for these new baud rates. table 3 shows the synchronization characters, delay times, and baud rates as they relate to e-clock frequency. commented boot rom listing listing 3. mc68hc711e9 bootloader rom contains a complete commented listing of the boot rom program in the mc68hc711e9 version of th e m68hc11. other versions can be found in appendix b of the m68hc11 reference manual . table 3. bootloader baud rates sync character timeout delay baud rates at e clock = 2 mhz 2.1 mhz 3 mhz 3.15 mhz 4 mhz 4.2 mhz $ff 4 characters 7812 8192 11,718 12,288 15,624 16,838 $ff 4 characters 1200 1260 1800 1890 2400 2520 $f0 4.9 characters 9600 10,080 14,400 15,120 19,200 20,160 $fd 17.3 characters 5208 5461 7812 8192 10,416 10,922 $fd 13 characters 3906 4096 5859 6144 7812 8192
m68hc11 bootstrap mode, rev. 1.1 222 freescale semiconductor listing 3. mc68hc711e9 bootloader rom listing 3. mc68hc 711e9 bootloader rom 1 **************************************************** 2 * bootloader firmware for 68hc711e9 - 21 aug 89 3 **************************************************** 4 * features of this bootloader are... 5 * 6 * auto baud select between 7812.5 and 1200 (8 mhz) 7 * 0 - 512 byte variable length download 8 * jump to eeprom at $b600 if 1st download byte = $00 9 * program - utility subroutine to program eprom 10 * upload - utility subroutine to dump memory to host 11 * mask i.d. at $bfd4 = $71e9 12 **************************************************** 13 * revision a - 14 * 15 * fixed bug in program routine where the first byte 16 * programmed into the eprom was not transmitted for 17 * verify. 18 * also added to program routine a skip of bytes 19 * which were already programmed to the value desired. 20 * 21 * this new version allows variable length download 22 * by quitting reception of characters when an idle 23 * of at least four character times occurs 24 * 25 **************************************************** 26 27 * equates for use with index offset = $1000 28 * 29 0008 portd equ $08 30 000e tcnt equ $0e 31 0016 toc1 equ $16 32 0023 tflg1 equ $23 33 * bit equates for tflg1 34 0080 oc1f equ $80 35 * 36 0028 spcr equ $28 (for dwom bit) 37 002b baud equ $2b 38 002d sccr2 equ $2d 39 002e scsr equ $2e 40 002f scdat equ $2f 41 003b pprog equ $3b 42 * bit equates for pprog 43 0020 elat equ $20 44 0001 epgm equ $01 45 * 46 47 * memory configuration equates 48 * 49 b600 eepmstr equ $b600 start of eeprom 50 b7ff eepmend equ $b7ff end of eeprom 51 *
listing 3. mc68hc711e9 bootloader rom m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 223 52 d000 eprmstr equ $d000 start of eprom 53 ffff eprmend equ $ffff end of eprom 54 * 55 0000 ramstr equ $0000 56 01ff ramend equ $01ff 57 58 * delay constants 59 * 60 0db0 delays equ 3504 delay at slow baud 61 021b delayf equ 539 delay at fast baud 62 * 63 1068 progdel equ 4200 2 ms programming delay 64 * at 2.1 mhz 65 66 **************************************************** 67 bf00 org $bf00 68 **************************************************** 69 70 * next two instructions provide a predictable place 71 * to call program and upload even if the routines 72 * change size in future versions. 73 * 74 bf00 7ebf13 program jmp prgrout eprom programming utility 75 bf03 upload equ * upload utility 76 77 **************************************************** 78 * upload - utility subroutine to send data from 79 * inside the mcu to the host via the sci interface. 80 * prior to calling upload set baud rate, turn on sci 81 * and set y=first address to upload. 82 * bootloader leaves baud set, sci enabled, and 83 * y pointing at eprom start ($d000) so these default 84 * values do not have to be changed typically. 85 * consecutive locations are sent via sci in an 86 * infinite loop. reset stops the upload process. 87 **************************************************** 88 bf03 ce1000 ldx #$1000 point to internal registers 89 bf06 18a600 uploop ldaa 0,y read byte 90 bf09 1f2e80fc brclr scsr,x $80 * wait for tdre 91 bf0d a72f staa scdat,x send it 92 bf0f 1808 iny 93 bf11 20f3 bra uploop next... 94 95 **************************************************** 96 * program - utility subroutine to program eprom. 97 * prior to calling program set baud rate, turn on sci 98 * set x=2ms prog delay constant, and set y=first 99 * address to program. sp must point to ram. 100 * bootloader leaves baud set, sci enabled, x=4200 101 * and y pointing at eprom start ($d000) so these 102 * default values don't have to be changed typically. 103 * delay constant in x should be equivalent to 2 ms 104 * at 2.1 mhz x=4200; at 1 mhz x=2000. 105 * an external voltage source is required for eprom 106 * programming.
m68hc11 bootstrap mode, rev. 1.1 224 freescale semiconductor listing 3. mc68hc711e9 bootloader rom 107 * this routine uses 2 bytes of stack space 108 * routine does not return. reset to exit. 109 **************************************************** 110 bf13 prgrout equ * 111 bf13 3c pshx save program delay constant 112 bf14 ce1000 ldx #$1000 point to internal registers 113 bf17 114 * send $ff to indicate ready for program data 115 116 bf17 1f2e80fc brclr scsr,x $80 * wait for tdre 117 bf1b 86ff ldaa #$ff 118 bf1d a72f staa scdat,x 119 120 bf1f wait1 equ * 121 bf1f 1f2e20fc brclr scsr,x $20 * wait for rdrf 122 bf23 e62f ldab scdat,x get received byte 123 bf25 18e100 cmpb $0,y see if already programmed 124 bf28 271d beq doneit if so, skip prog cycle 125 bf2a 8620 ldaa #elat put eprom in prog mode 126 bf2c a73b staa pprog,x 127 bf2e 18e700 stab 0,y write the data 128 bf31 8621 ldaa #elat+epgm 129 bf33 a73b staa pprog,x turn on prog voltage 130 bf35 32 pula pull delay constant 131 bf36 33 pulb into d-reg 132 bf37 37 pshb but also keep delay 133 bf38 36 psha keep delay on stack 134 bf39 e30e addd tcnt,x delay const + present tcnt 135 bf3b ed16 std toc1,x schedule oc1 (2ms delay) 136 bf3d 8680 ldaa #oc1f 137 bf3f a723 staa tflg1,x clear any previous flag 138 139 bf41 1f2380fc brclr tflg1,x oc1f * wait for delay to expire 140 bf45 6f3b clr pprog,x turn off prog voltage 141 * 142 bf47 doneit equ * 143 bf47 1f2e80fc brclr scsr,x $80 * wait for tdre 144 bf4b 18a600 ldaa $0,y read from eprom and... 145 bf4e a72f staa scdat,x xmit for verify 146 bf50 1808 iny point at next location 147 bf52 20cb bra wait1 back to top for next 148 * loops indefinitely as long as more data sent. 149 150 **************************************************** 151 * main bootloader starts here 152 **************************************************** 153 * reset vector points to here 154 155 bf54 begin equ * 156 bf54 8e01ff lds #ramend initialize stack pntr 157 bf57 ce1000 ldx #$1000 point at internal regs 158 bf5a 1c2820 bset spcr,x $20 select port d wire-or mode 159 bf5d cca20c ldd #$a20c baud in a, sccr2 in b 160 bf60 a72b staa baud,x scpx = 4, scrx = 4 161 * writing 1 to msb of baud resets count chain
listing 3. mc68hc711e9 bootloader rom m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 225 162 bf62 e72d stab sccr2,x rx and tx enabled 163 bf64 cc021b ldd #delayf delay for fast baud rate 164 bf67 ed16 std toc1,x set as default delay 165 166 * send break to signal ready for download 167 bf69 1c2d01 bset sccr2,x $01 set send break bit 168 bf6c 1e0801fc brset portd,x $01 * wait for rxd pin to go low 169 bf70 1d2d01 bclr sccr2,x $01 clear send break bit 170 bf73 171 bf73 1f2e20fc brclr scsr,x $20 * wait for rdrf 172 bf77 a62f ldaa scdat,x read data 173 * data will be $00 if break or $00 received 174 bf79 2603 bne notzero bypass jmp if not 0 175 bf7b 7eb600 jmp eepmstr jump to eeprom if it was 0 176 bf7e notzero equ * 177 bf7e 81ff cmpa #$ff $ff will be seen as $ff 178 bf80 2708 beq baudok if baud was correct 179 * or else change to 104 (13 & 8) 1200 @ 2mhz 180 bf82 1c2b33 bset baud,x $33 works because $22 -> $33 181 bf85 cc0db0 ldd #delays and switch to slower... 182 bf88 ed16 std toc1,x delay constant 183 bf8a baudok equ * 184 bf8a 18ce0000 ldy #ramstr point at start of ram 185 186 bf8e wait equ * 187 bf8e ec16 ldd toc1,x move delay constant to d 188 bf90 wtloop equ * 189 bf90 1e2e2007 brset scsr,x $20 newone exit loop if rdrf set 190 bf94 8f xgdx swap delay count to x 191 bf95 09 dex decrement count 192 bf96 8f xgdx swap back to d 193 bf97 26f7 bne wtloop loop if not timed out 194 bf99 200f bra star quit download on timeout 195 196 bf9b newone equ * 197 bf9b a62f ldaa scdat,x get received data 198 bf9d 18a700 staa $00,y store to next ram location 199 bfa0 a72f staa scdat,x transmit it for handshake 200 bfa2 1808 iny point at next ram location 201 bfa4 188c0200 cpy #ramend+1 see if past end 202 bfa8 26e4 bne wait if not, get another 203 204 bfaa star equ * 205 bfaa ce1068 ldx #progdel init x with programming delay 206 bfad 18ced000 ldy #eprmstr init y with eprom start addr 207 bfb1 7e0000 jmp ramstr ** exit to start of ram ** 208 bfb4 209 **************************************************** 210 * block fill unused bytes with zeros 211 212 bfb4 000000000000 bsz $bfd1-* 000000000000 000000000000 000000000000 0000000000
m68hc11 bootstrap mode, rev. 1.1 226 freescale semiconductor listing 3. mc68hc711e9 bootloader rom 213 214 **************************************************** 215 * boot rom revision level in ascii 216 * (org $bfd1) 217 bfd1 41 fcc "a" 218 **************************************************** 219 * mask set i.d. ($0000 for eprom parts) 220 * (org $bfd2) 221 bfd2 0000 fdb $0000 222 **************************************************** 223 * '711e9 i.d. - can be used to determine mcu type 224 * (org $bfd4) 225 bfd4 71e9 fdb $71e9 226 227 **************************************************** 228 * vectors - point to ram for pseudo-vector jumps 229 230 bfd6 00c4 fdb $100-60 sci 231 bfd8 00c7 fdb $100-57 spi 232 bfda 00ca fdb $100-54 pulse accum input edge 233 bfdc 00cd fdb $100-51 pulse accum overflow 234 bfde 00d0 fdb $100-48 timer overflow 235 bfe0 00d3 fdb $100-45 timer output compare 5 236 bfe2 00d6 fdb $100-42 timer output compare 4 237 bfe4 00d9 fdb $100-39 timer output compare 3 238 bfe6 00dc fdb $100-36 timer output compare 2 239 bfe8 00df fdb $100-33 timer output compare 1 240 bfea 00e2 fdb $100-30 timer input capture 3 241 bfec 00e5 fdb $100-27 timer input capture 2 242 bfee 00e8 fdb $100-24 timer input capture 1 243 bff0 00eb fdb $100-21 real time int 244 bff2 00ee fdb $100-18 irq 245 bff4 00f1 fdb $100-15 xirq 246 bff6 00f4 fdb $100-12 swi 247 bff8 00f7 fdb $100-9 illegal op-code 248 bffa 00fa fdb $100-6 cop fail 249 bffc 00fd fdb $100-3 clock monitor 250 bffe bf54 fdb begin reset 251 c000 end symbol table: symbol name value def.# line number cross reference baud 002b *00037 00160 00180 baudok bf8a *00183 00178 begin bf54 *00155 00250 delayf 021b *00061 00163 delays 0db0 *00060 00181 doneit bf47 *00142 00124 eepmend b7ff *00050 eepmstr b600 *00049 00175 elat 0020 *00043 00125 00128 epgm 0001 *00044 00128 eprmend ffff *00053 eprmstr d000 *00052 00206
listing 3. mc68hc711e9 bootloader rom m68hc11 bootstrap mode, rev. 1.1 freescale semiconductor 227 newone bf9b *00196 00189 notzero bf7e *00176 00174 oc1f 0080 *00034 00136 00139 portd 0008 *00029 00168 pprog 003b *00041 00126 00129 00140 prgrout bf13 *00110 00074 progdel 1068 *00063 00205 program bf00 *00074 ramend 01ff *00056 00156 00201 ramstr 0000 *00055 00184 00207 sccr2 002d *00038 00162 00167 00169 scdat 002f *00040 00091 00118 00122 00145 00172 00197 00199 scsr 002e *00039 00090 00116 00121 00143 00171 00189 spcr 0028 *00036 00158 star bfaa *00204 00194 tcnt 000e *00030 00134 tflg1 0023 *00032 00137 00139 toc1 0016 *00031 00135 00164 00182 00187 upload bf03 *00075 uploop bf06 *00089 00093 wait bf8e *00186 00202 wait1 bf1f *00120 00147 wtloop bf90 *00188 00193 errors: none labels: 35 last program address: $bfff last storage address: $0000 program bytes: $0100 256 storage bytes: $0000 0
m68hc11 bootstrap mode, rev. 1.1 228 freescale semiconductor listing 3. mc68hc711e9 bootloader rom
? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor engineering bulletin eb184 rev. 0.1, 07/2005 enabling the security feature on the mc68hc711e9 devices with pcbug11 on the m68hc711e9pgmr by edgar saenz austin, texas introduction the pcbug11 software, needed along with the m68hc711e9pgmr to program mc68hc711e9 devices, is available from the download section of the microcontroller worldwide web site: http://www.freescale.com retrieve the file pcbug342.exe (a self-extracting archive) from the mcu11 directory. some freescale evaluation board products also are shipped with pcbug11. note for specific information about any of the pcbug11 commands, see the appropriate sections in the pcbug11 user's manual (part number m68pcbug11/d2), which is available from the freescale literature distribution center, as well as the worldwide web at http://www.freescale.com . the file is also on the software download system and is called pcbug11.pdf.
enabling the security feature on the mc68hc711e9 de vices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 230 freescale semiconductor to execute the program to execute th e program use this step-by-step procedure to program the mc68hc711e9 device. step 1 before applying power to the programming board, connect the m68hc711e9pgmr serial port p2 to one of your pc com ports with a standard 25- pin rs-232 cable. do not use a null modem cable or adapter which swaps the transmit and receiv e signals between the connectors at each end of the cable. place the mc68hc711e9 part in the plcc socket on your board. insert the part upside down with the notched corner pointing toward the red power led. make sure both s1 and s2 switches are turned off. apply +5 volts to +5-v, +12 volts (at most +12.5 volts) to v pp , and ground to gnd on your programmer board?s power connector, p1. the remaining txd/pd1 and rxd/pd0 connections are not used in this procedure. they are for gang programming mc68hc711e9 devices, which is discussed in the m68hc711e9pgmr manual . you cannot gang program with pcbug11. ensure that the "remove for multi-programming" jumper, j1, below the +5-v power switch has a fabricated jumper installed. step 2 apply power to the programmer board by moving the +5-v switch to the on position. from a dos command line prompt, start pcbug11this way: c:\pcbug11\ > pcbug11 ?e port = 1 with the e9pgmr connected to com1 or c:\pcbug11\ > pcbug11 ?e port = 2 with the e9pgmr connected to com2 pcbug11 only supports com ports 1 and 2. if the proper connections are made and you have a high-quality cable, you should quickly get a pc bug11 command prompt. if you do receive a comms fault error, check the cable and board connections. mo st pcbug11 communications problems can be traced to poorly made cables or bad board connections. step 3 pcbug11 defaults to base 10 for its input parameters. change this to hexadecimal by typing: control base hex. step 4 clear the block protect register (bprot) to allow programming of the mc68hc711e9 eeprom. at the pcbug11 command prompt, type: ms 1035 00.
to execute the program enabling the security feature on the mc68hc711e9 de vices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 freescale semiconductor 231 step 5 the config register defaults to hexadecimal 103f on the mc68hc711e9. pcbug11 needs adressing parameters to allow programming of a specific block of memory so the following parameter must be given. at the pcbug11 command pr ompt, type: eeprom 0. then type: eeprom 103f 103f. step 6 erase the config to allow byte programming. at the pcbug11 command prompt, type: eeprom erase bulk 103f. step 7 you are now ready to download the program into the eeprom and eprom. at the pcbug11command prompt, type: loadsc:\myprog\myprog.s19. for more details on programming the eprom, read the engineering bulletin programming mc68hc711e9 devices with pcbug11 and the m68hc11evb , freescale document number eb187. step 8 you are now ready to enable the security feature on the mchc711e9. at the pcbug11 command prompt type: ms 103f 05. step 9 after the programming operation is complete, verify ng the config on the mchc711e9 is not possible because in bootstrap mode the default value is always forced. step 10 the part is now in secure mode and whatever code you loaded into eepr om will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode. note it is important to note that the microcontroller will work properly in secure mode only in single chip mode. note if the part is placed in bootstrap or expanded, the code in eeprom and ram will be erased and the microcontroller cannot be reused. the security software will constantly read the nosec bit and lock the part.
enabling the security feature on the mc68hc711e9 de vices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 232 freescale semiconductor to execute the program
? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor engineering bulletin eb188 rev. 0.1, 07/2005 enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr by edgar saenz austin, texas introduction the pcbug11 software, needed along with the m68hc711e9pgmr to program mc68hc811e2 devices, is available from the download section of the microcontroller worldwide web site http://www.freescale.com retrieve the file pcbug342.exe (a self-extracting archive) from the mcu11 directory. some freescale evaluation board products also are shipped with pcbug11. note for specific information about any of the pcbug11 commands, see the appropriate sections in the pcbug11 user's manual (part number m68pcbug11/d2), which is available from the freescale literature http://www.freescale.com . the file is also on the software download system and is called pcbug11.pdf.
enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 234 freescale semiconductor to execute the program to execute th e program once you have obtained pcbug11, use this step-by-step procedure. step 1 before applying power to the programming board, connect the m68hc711e9pgmr serial port p2 to one of your pc com ports with a standard 25 pin rs-232 cable. do not use a null modem cable or adapter which swaps the transmit and receiv e signals between the connectors at each end of the cable. place your mc68hc811e2 part in the plcc socket on your board. insert the part upside down with the notched corner pointing toward the red power led. make sure both s1 and s2 switches are turned off. apply +5 volts to +5 volts and ground to gnd on the programmer board?s power connector, p1. applying voltage to the v pp pin is not necessary. step 2 apply power to the programmer board by moving the +5-volt switch to the on position. from a dos command line prompt, start pcbug11 this way: c:\pcbug11\> pcbug11 ?a port = 1 when the e9pgmr connected to com1 or c:\pcbug11\> pcbug11 ?a port = 2 w hen the e9pgmr connected to com2 pcbug11only supports com ports 1 and 2. step 3 pcbug11 defaults to base ten for its input parameters. change this to hexadecimal by typing: control base hex step 4 clear the block protect register (bprot) to allow programming of the mc68hc811e2 eeprom. at the pcbug11 command prompt, type: ms 1035 00 step 5 pcbug11 defaults to a 512-byte eeprom array loca ted at $b600. this must be changed since the eeprom is, by default, located at $f800 on the mc68hc811e2. at the pcbug11 command prompt, type: eeprom 0 then type: eeprom f800 ffff then type: eeprom 103f 103f this assumes you have not relocated the eeprom by previously reprogramming the upper 4 bits of the config register. but if you have done this and your s records reside in an address range other than $f800 to $ffff, you will need to first relocate the eeprom.
to execute the program enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 freescale semiconductor 235 step 6 erase the config to allow programming of nosec bit (bit 3). it is also recommended to program the eeprom at this point before programming the conf ig register. refer to the engineering bulletin programming mc68hc811e2 devices with pcbug11 and the m68hc711e9pgmr , freescale document number eb184. at the pcbug11command prompt, type: eeprom erase bulk 103f step 7 you are now ready to enable the security feature on the mchc811e2. at the pcbug11 command prompt, type: ms 103f 05 the value $05 assumes the eeprom is to be mapped from $0800 to $0fff. step 8 after the programming operation is complete, verify ing the config on the mchc811e2 is not possible because in bootstrap mode the default value is always forced. step 9 the part is now in secure mode and whatever code you loaded into eepr om will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode. the microcontroller will work properly in the secure mode only in single chip mode. note if the part is placed in bootstrap mode or expanded mode, the code in eeprom and ram will be erased the mi crocontroller can be reused.
enabling the security feature on m68hc811e2 devices with pcbug11 on the m68hc711e9pgmr, rev. 0.1 236 freescale semiconductor to execute the program
? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor engineering bulletin eb296 rev. 0.1, 07/2005 programming mc68hc711e9 devices with pcbug11 and the m68hc11evbu by john bodnar austin, texas introduction the pcbug1software, needed along with the m68h c11evbu to program mc68hc711e9 devices, is available from the download section of the microcontroller worldwide web site http://www.freescale.com retrieve the file pcbug342.exe (a self-extracting archive) from the mcu11 directory. some freescale evaluation board products also are shipped with pcbug11. note for specific information about any of the pcbug11 commands, see the appropriate sections in the pcbug11 user's manual (part number m68pcbug11/d2), which is available from the freescale literature distribution center, as well as the worldwide web at http://www.freescale.com . the file is also on the software download system and is called pcbug11.pdf.
programming mc68hc711e9 devices with pc bug11 and the m68hc11evbu, rev. 0.1 238 freescale semiconductor programming procedure programming procedure once you have obtained pcbug11, use this step-by- step procedure to program your mc68hc711e9 part. step 1 before applying power to the evbu, remove the ju mper from j7 and place it across j3 to ground the modb pin. place a jumper across j4 to ground the moda pin. this will force the evbu into special bootstrap mode on power up. remove the resident mc68hc11e9 mcu from the evbu. place your mc68hc711e9 in the open socket with t he notched corner of the part aligned with the notch on the plcc socket. connect the evbu to one of your pc com ports. apply +5 volts to v dd and ground to gnd on the power connector of your evbu. also take note of p4 connector pin 18. in step 5, you will connect a +12-volt (at most +12.5 volts) programming voltage through a 100- ? current limiting resistor to the xirq pin. do not connect this programming voltage until you are instructed to do so in step 5. step 2 from a dos command line prompt, start pcbug11 with ? c:\pcbug11\> pcbug11 ?e port = 1 with the evbu connected to com1 ? c:\pcbug11\> pcbug11 ?e port = 2 with the evbu connected to com2 pcbug11 only supports com ports 1 and 2. if you ha ve made the proper connections and have a high quality cable, you should quickly ge t a pcbug11 command prompt. if you do receive a comms fault error, check your cable and board connections. most pc bug11 communications problems can be traced to poorly made cables or bad board connections. step 3 pcbug11 defaults to base 10 for its input para meters; change this to hexadecimal by typing control base hex step 4 you must declare the addresses of the eprom array to pcbug11. to do this, type: eprom d000 ffff step 5 you are now ready to download your program into the eprom. connect +12 volts (at most +12.5 volts) through a 100- ? current limiting resistor to p4 connector pin 18, the xirq* pin. at the pcbug11 command prompt ty pe: loads c:\myprog\ishere.s19 substitute the name of your program into the command above. use a full path name if your program is not located in the same directory as pcbug11.
programming procedure programming mc68hc711e9 devices with pc bug11 and the m68hc11evbu, rev. 0.1 freescale semiconductor 239 step 6 after the programming operation is complete, pcbug11 will display this message total bytes loaded: $xxxx total bytes programmed: $yyyy you should now remove the programming voltag e from p4 connector pin 18, the xirq* pin. each org directive in your assembly language s ource will cause a pair of these lines to be generated. for this operation, $yyyy will be in cremented by the size of each block of code programmed into the eprom of the mc68hc711e9. pcbug11 will display the above message whet her or not the programming operation was successful. as a precaution, you s hould have pcbug11 verify your code. at the pcbug11 command prompt type: verf c:\myprog\ishere.s19 substitute the name of your program into the command above. use a full path name if your program is not located in the same directory as pcbug11. if the verify operation fails, a list of addresses which did not program correctly is displayed. should this occur, you probably need to erase your part more completely. to do so, allow the mc68hc711e9 to sit for at least 45 minutes under an ultraviolet light s ource. attempt the programming operation again. if you have purchased devices in plastic packages (one-t ime programmable parts), you will need to try again with a new, unprogrammed device.
programming mc68hc711e9 devices with pc bug11 and the m68hc11evbu, rev. 0.1 240 freescale semiconductor programming procedure

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